Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
Field
GT Block Timer
Count
GT Block Timer
Offset
GT Block Timer
Structure[]
Byte
Length
Byte
Offset
4 12 Number of Timers implemented in this GT Block ('n'). . Must be
less than or equal to 8.
4 16 Offset to the Platform Timer Structure array from the start of this
structure
n*40 GT
Block
Timer
Offset
Description
Array of GT Block Timer Structures. See Table 5-121.
Table 5-121 GT Block Timer Structure Format
Field
Byte
Length
Byte
Offset
Description
GT Frame Number 1 0 The frame number (0-7) for this timer (‘x’)
Reserved 3 1 Must be zero
GTx Physical
Address
(CntBaseX)
8 4 Physical Address at which the CntBase block for GTx is located
GTx Physical
Address
(CntEL0BaseX)
GTx Physical Timer
GSIV
GTx Physical Timer
Flags
GTx Virtual Timer
GSIV
GTx Virtual Timer
Flags
8 12 Physical Address at which the CntEL0Base block for GTx is
located. If this block is not implemented for GTx, must be
0xFFFFFFFFFFFFFFFF.
4 20 GSIV for the GTx physical timer
4 24 Flags for the GTx physical timer. See Table 5-122
4 28 GSIV for the GTx virtual timer If the Virtual Timer is not
implemented for GTx, this field must be 0.
4 32 Flags for the GTx virtual timer, if implemented. See Table 5-122.
GTx Common Flags 4 36 See Table 5-123.
Table 5-122 Flag Definitions: GT Block Physical Timers and Virtual timers
Bit Field
Timer interrupt
Mode
Timer Interrupt
polarity
Bit
Offset
Number
of bits
Description
0 1 This bit indicates the mode of the timer interrupt
1: Interrupt is Edge triggered
0: Interrupt is Level triggered
1 1 This bit indicates the polarity of the timer interrupt
1: Interrupt is Active low
0: Interrupt is Active high
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