Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
Field
Reserved 4 44 Must be zero
Secure EL1 timer
GSIV
Secure EL1 timer
Flags
Non-Secure EL1
timer GSIV
Non-Secure EL1
timer Flags
4 48 GSIV for the secure EL1 physical timer. This value is optional. If
not provided, this field must be 0.
4 52 Flags for the secure EL1 physical timer (defined below). If the
"Secure EL1 timer GSIV" field (above) is 0, this field must be 0.
4 56 GSIV for the non-secure EL1 timer physical timer interrupt
4 60 Flags for the non-secure EL1 physical timer (defined below)
Virtual timer GSIV 4 64 GSIV for the non-secure virtual timer interrupt
Virtual Timer Flags 4 68 Flags for the virtual timer (defined below)
Non-Secure EL2 4 72 GSIV for the Non-Secure EL2 physical timer
timer GSIV
Non-Secure EL2
timer Flags
4 76 Flags for the Non-Secure EL2 physical timer(defined below)
CntReadBase
Physical address
8 80 The 64-bit physical address at which the Counter Read block is
located
Platform Timer Count 4 88 Number of entries in the Platform Timer Structure[] array
Platform Timer Offset 4 92 Offset to the Platform Timer Structure[] array from the start of
this table
Platform Timer
Structure[]
Byte
Length
Byte
Offset
--- Platfor
m
Timer
Offset
Description
Array of Platform Timer Type structures describing memorymapped
Timers available on this platform. These structures are
described in the below sections.
Secure EL1 timer Flags, Non-Secure EL1 timer flags, Virtual Timer Flags, and EL2 timer Flags all
have the same definition.
Table 5-118 Flag Definitions: Virtual Timer, EL2 timers, and Secure & Non-Secure EL1 timers
Bit Field
Timer interrupt
Mode
Timer Interrupt
polarity
Bit
Offset
Number
of bits
Description
0 1 This bit indicates the mode of the timer interrupt
1: Interrupt is Edge triggered
0: Interrupt is Level triggered
1 1 This bit indicates the polarity of the timer interrupt
1: Interrupt is Active low
0: Interrupt is Active high
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