Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
Field
Memory Controller
Structure [n]
Byte
Length
Byte
Offset
Description
--- 12 A list of Memory Controller Structures.This list provides
information on the memory controllers present in the socket. See
Table 5-101.
Table 5-101 Memory Controller Structure
Field
Byte
Length
Byte
Offset
Description
Type 1 0 1 – Memory Controller
Reserved 1 1 Reserved, must be zero.
Length 2 2 Length in bytes for this Structure. The length implies the
number of physical component identifier structures at the
end of this structure.
Flag 2 4 Bit [0] – set to 1 to indicate that this is a top level aggregator
device.
Bit [1] – set to 1 to indicate physical element of the topology.
Set to 0 to indicate logical element of topology
Bit [2] and [3] –
• If 00, indicates that all components aggregated by this
device implements volatile memory
• If 01, indicates that components aggregated by this
device implements both volatile and non-volatile memory
• If 10, indicates that all components aggregated by this
device implements non-volatile memory
• 11 - Reserved
Bit [4] – Bit [15] Reserved
Reserved 2 6 Reserved, must be zero.
Read Latency
(typical)
4 8 In nanoseconds as seen at the controller for a cacheline
access.
Write latency (typical) 4 12 In nanoseconds as seen at the controller for a cacheline
access.
Read Bandwidth 4 16 In MB/s
(typical)
Write Bandwidth 4 20 In MB/s
(typical)
Optimal access unit 2 24 In bytes
Optimal access 2 26 In bytes
alignment
Reserved 2 28 Reserved , must be zero.
Number of Proximity
Domains (m)
2 30 Number of Proximity Domains that immediately follow. A
zero in this field indicates that proximity domain information
is not provided by the platform and that no 4-byte domains
follow
186 April, 2015 Version 6.0