Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
Table 5-92 Command Status
Field
Bit
Length
Bit
Offset
Description
Command 1 0 If set, the platform has completed processing the last command.
Complete
SCI Doorbell 1 1 If set, then this PCC Sub-Channel has signaled the SCI door
bell. In Response to this SCI, OSPM should probe the
Command Complete and the Platform Notification fields to
determine the cause of SCI.
Error 1 2 If set, an error occurred executing the last command.
Platform
1 3 Indicates that the SCI doorbell was invoked by the platform.
Notification
Reserved 12 4 Reserved.
5.2.21.3 Action Sequence
SetMemoryPowerState: The following sequence needs to be done to set a memory power state
1. Write target POWER NODE ID value to MEMORY_POWER_NODE_ID register of PCC sub
channel.
2. Write desired POWER STATE ID value to POWER STATE ID register of PCC sub channel .
3. Write SET (See Table 5-90) to MEMORY_POWER_STATE register of PCC sub channel.
4. Write PCC EXECUTE (See Table 5-89) to PCC Command register for the PCC sub channel.
5. OSPM rings the door bell by writing to Doorbell register.
6. Platform completes the request and will generate SCI to indicate that the command is complete.
7. OSPM reads the Status register for the PCC sub channel and confirms that the command was
successfully completed.
GetMemoryPowerState: The following sequence needs to be done to get the current memory power
state
1. Write target POWER NODE ID value to MEMORY_POWER_NODE_ID register of PCC sub
channel.
2. Write GET (See Table 5-90) to MEMORY_POWER_STATE register of PCC sub channel.
3. Write PCC EXECUTE (See Table 5-89) to PCC Command register for the PCC sub channel.
4. OSPM rings the door bell by writing to Doorbell register.
5. Platform completes the request and will generate SCI to indicate that command is complete.
6. OSPM reads Status register for the PCC sub channel and confirms that the command was
successfully completed.
7. OSPM reads POWER STATE from POWER_STATE_ID register of PCC sub channel.
5.2.21.4 Memory Power Node
Memory Power Node is a representation of a logical memory region that needs to be transitioned in
and out of a memory power state as a unit. This logical memory region is made up of one more
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