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Advanced Configuration and Power Interface Specification

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<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

Table 5-67 GIC Interrupt Translation Service Structure<br />

Field<br />

Byte<br />

Length<br />

Byte<br />

Offset<br />

Description<br />

Type 1 0 0xF GIC ITS structure<br />

Length 1 1 16<br />

Reserved 2 2 Reserved - Must be zero<br />

GIC ITS ID 4 4 GIC ITS ID. In a system with multiple GIC ITS units, this value must<br />

be unique to each one.<br />

Physical Base 8 8 The 64-bit physical address for the Interrupt Translation Service<br />

Address<br />

Reserved 4 16 Reserved – Must be zero<br />

5.2.13 Global System Interrupts<br />

Global System Interrupts can be thought of as ACPI Plug <strong>and</strong> Play IRQ numbers. They are used to<br />

virtualize interrupts in tables <strong>and</strong> in ASL methods that perform resource allocation of interrupts. Do<br />

not confuse global system interrupts with ISA IRQs although in the case of the IA-PC 8259<br />

interrupts they correspond in a one-to-one fashion.<br />

There are two interrupt models used in ACPI-enabled systems.<br />

The first model is the APIC model. In the APIC model, the number of interrupt inputs supported by<br />

each I/O APIC can vary. OSPM determines the mapping of the Global System Interrupts by<br />

determining how many interrupt inputs each I/O APIC supports <strong>and</strong> by determining the global<br />

system interrupt base for each I/O APIC as specified by the I/O APIC Structure. OSPM determines<br />

the number of interrupt inputs by reading the Max Redirection register from the I/O APIC. The<br />

global system interrupts mapped to that I/O APIC begin at the global system interrupt base <strong>and</strong><br />

extending through the number of interrupts specified in the Max Redirection register. This mapping<br />

is depicted in Figure 5-25.<br />

There is exactly one I/O APIC structure per I/O APIC in the system.<br />

154 April, 2015 Version 6.0

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