Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
Global System Interrupt Vector
(ie ACPI PnP IRQ# )
Interrupt Input Lines
on IOAPIC
‘System Vector Base’
reported in IOAPIC Struc
24 input
IOAPIC
16 input
IOAPIC
24 input
IOAPIC
0 INTI_0 0
.
.
.
23 INTI_23
24 INTI_0 24
.
.
.
39 INTI_15
40 INTI_0 40
.
51 INTI_11
.
55 INTI_23
5.2.12.14 GICC Structure
Figure 5-25 APIC–Global System Interrupts
In the GICC interrupt model, logical processors are required to have a Processor Device object in the
DSDT, and must convey each processor’s GICC information to the OS using the GICC structure.
The format of the GICC structure is shown in Table 5-61.
Table 5-61 GICC Structure Format
Field
Byte
Length
Byte
Offset
Description
Type 1 0 0xB GICC structure
Length 1 1 80
Reserved 2 2 Reserved - Must be zero
CPU Interface
Number
4 4 GIC's CPU Interface Number. In GICv1/v2 implementations, this
value matches the bit index of the associated processor in the GIC
distributor's GICD_ITARGETSR register.
For GICv3/4 implementations this field must be provided by the
platform, if compatibility mode is supported.
If it is not supported by the implementation, then this field must be
zero.
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