Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
INIT messages cause processors to soft reset.
If a platform can generate an interrupt after correcting platform errors (e.g., single bit error
correction), the interrupt input line used to signal such corrected errors is specified by the Global
System Interrupt field in the following table. Some systems may restrict the retrieval of corrected
platform error information to a specific processor. In such cases, the firmware indicates the
processor that can retrieve the corrected platform error information through the Processor ID and
EID fields in the structure below. OSPM is required to program the I/O SAPIC redirection table
entries with the Processor ID, EID values specified by the ACPI system firmware. On platforms
where the retrieval of corrected platform error information can be performed on any processor, the
firmware indicates this capability by setting the CPEI Processor Override flag in the Platform
Interrupt Source Flags field of the structure below. If the CPEI Processor Override Flag is set,
OSPM uses the processor specified by Processor ID, and EID fields of the structure below only as a
target processor hint and the error retrieval can be performed on any processor in the system.
However, firmware is required to specify valid values in Processor ID, EID fields to ensure
backward compatibility.
If the CPEI Processor Override flag is clear, OSPM may reject a ejection request for the processor
that is targeted for the corrected platform error interrupt. If the CPEI Processor Override flag is set,
OSPM can retarget the corrected platform error interrupt to a different processor when the target
processor is ejected.
Note that the _MAT object can return a buffer containing Platform Interrupt Source Structure
entries. It is allowed for such an entry to refer to a Global System Interrupt that is already specified
by a Platform Interrupt Source Structure provided through the static MADT table, provided the
value of platform interrupt source flags are identical.
Refer to the Itanium TM Processor Family System Abstraction Layer (SAL) Specification for details
on handling the Corrected Platform Error Interrupt.
Table 5-57 Platform Interrupt Sources Structure
Field
Byte
Length
Byte
Offset
Description
Type 1 0 8 Platform Interrupt Source structure
Length 1 1 16
Flags 2 2 MPS INTI flags. See Table 5-51 for a description of this field.
Interrupt Type 1 4 1 PMI
2 INIT
3 Corrected Platform Error Interrupt
All other values are reserved.
Processor ID 1 5 Processor ID of destination.
Processor EID 1 6 Processor EID of destination.
I/O SAPIC Vector 1 7 Value that OSPM must use to program the vector field of the I/O
SAPIC redirection table entry for entries with the PMI interrupt type.
Global System
Interrupt
4 8 The Global System Interrupt that this platform interrupt will signal.
Platform Interrupt
Source Flags
4 12 Platform Interrupt Source Flags. See Table 5-58 for a description of
this field
146 April, 2015 Version 6.0