Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
Interrupt Source Overrides are also necessary when an identity mapped interrupt input has a nonstandard
polarity.
Note: You must have an interrupt source override entry for the IRQ mapped to the SCI interrupt if this
IRQ is not identity mapped. This entry will override the value in SCI_INT in FADT. For example, if
SCI is connected to IRQ 9 in PIC mode and IRQ 9 is connected to INTIN11 in APIC mode, you
should have 9 in SCI_INT in the FADT and an interrupt source override entry mapping IRQ 9 to
INTIN11.
5.2.12.6 Non-Maskable Interrupt Source Structure
This structure allows a platform designer to specify which I/O (S)APIC interrupt inputs should be
enabled as non-maskable. Any source that is non-maskable will not be available for use by devices.
Table 5-52 Non-maskable Source Structure
Field
Byte
Length
Byte
Offset
Description
Type 1 0 3 NMI
Length 1 1 8
Flags 2 2 Same as MPS INTI flags
Global System
Interrupt
4 4 The Global System Interrupt that this NMI will signal.
5.2.12.7 Local APIC NMI Structure
This structure describes the Local APIC interrupt input (LINTn) that NMI is connected to for each of
the processors in the system where such a connection exists. This information is needed by OSPM to
enable the appropriate local APIC entry.
Each Local APIC NMI connection requires a separate Local APIC NMI structure. For example, if
the platform has 4 processors with ID 0-3 and NMI is connected LINT1 for processor 3 and 2, two
Local APIC NMI entries would be needed in the MADT.
Table 5-53 Local APIC NMI Structure
Field
Byte
Length
Byte
Offset
Description
Type 1 0 4 Local APIC NMI Structure
Length 1 1 6
ACPI Processor
UID
1 2 Value corresponding to the _UID listed in the processor’s device
object, or the Processor ID corresponding to the ID listed in the
processor object. A value of 0xFF signifies that this applies to all
processors in the machine.
Note that the use of the Processor declaration operator is
deprecated. See the compatibility note in Section 5.2.12.12 and
see Section 19.6.102, “Processor (Declare Processor).”
Flags 2 3 MPS INTI flags. See Table 5-51 for a description of this field.
Local APIC LINT# 1 5 Local APIC interrupt input LINTn to which NMI is connected.
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