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Advanced Configuration and Power Interface Specification

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<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

It is assumed that the ISA interrupts will be identity-mapped into the first I/O APIC sources. Most<br />

existing APIC designs, however, will contain at least one exception to this assumption. The Interrupt<br />

Source Override Structure is provided in order to describe these exceptions. It is not necessary to<br />

provide an Interrupt Source Override for every ISA interrupt. Only those that are not identitymapped<br />

onto the APIC interrupt inputs need be described.<br />

Note: This specification only supports overriding ISA interrupt sources.<br />

For example, if your machine has the ISA Programmable Interrupt Timer (PIT) connected to ISA<br />

IRQ 0, but in APIC mode, it is connected to I/O APIC interrupt input 2, then you would need an<br />

Interrupt Source Override where the source entry is ‘0’ <strong>and</strong> the Global System Interrupt is ‘2.’<br />

Table 5-50 Interrupt Source Override Structure<br />

Field<br />

Byte<br />

Length<br />

Byte<br />

Offset<br />

Description<br />

Type 1 0 2 Interrupt Source Override<br />

Length 1 1 10<br />

Bus 1 2 0 Constant, meaning ISA<br />

Source 1 3 Bus-relative interrupt source (IRQ)<br />

Global System<br />

Interrupt<br />

4 4 The Global System Interrupt that this bus-relative interrupt source<br />

will signal.<br />

Flags 2 8 MPS INTI flags. See Table 5-51 for a description of this field.<br />

The MPS INTI flags listed in Table 5-51 are identical to the flags used in Table 4-10 of the MPS<br />

version 1.4 specifications. The Polarity flags are the PO bits <strong>and</strong> the Trigger Mode flags are the EL<br />

bits.<br />

Table 5-51 MPS INTI Flags<br />

Local APIC -<br />

Flags<br />

Bit<br />

Length<br />

Bit<br />

Offset<br />

Description<br />

Polarity 2 0 Polarity of the APIC I/O input signals:<br />

00 Conforms to the specifications of the bus<br />

(For example, EISA is active-low for level-triggered interrupts)<br />

01 Active high<br />

10 Reserved<br />

11 Active low<br />

Trigger Mode 2 2 Trigger mode of the APIC I/O Input signals:<br />

00 Conforms to specifications of the bus<br />

(For example, ISA is edge-triggered)<br />

01 Edge-triggered<br />

10 Reserved<br />

11 Level-triggered<br />

Reserved 12 4 Must be zero.<br />

142 April, 2015 Version 6.0

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