27.10.2015 Views

Advanced Configuration and Power Interface Specification

ACPI_6.0

ACPI_6.0

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

ACPI Software Programming Model<br />

Enabled 1 0 If zero, this processor is unusable, <strong>and</strong> the operating system<br />

support will not attempt to use it.<br />

Reserved 31 1 Must be zero.<br />

5.2.12.3 I/O APIC Structure<br />

In an APIC implementation, there are one or more I/O APICs. Each I/O APIC has a series of<br />

interrupt inputs, referred to as INTIn, where the value of n is from 0 to the number of the last<br />

interrupt input on the I/O APIC. The I/O APIC structure declares which global system interrupts are<br />

uniquely associated with the I/O APIC interrupt inputs. There is one I/O APIC structure for each I/O<br />

APIC in the system. For more information on global system interrupts see Section 5.2.13, “Global<br />

System Interrupts.”<br />

Table 5-49 I/O APIC Structure<br />

Field<br />

Byte<br />

Length<br />

Byte<br />

Offset<br />

Description<br />

Type 1 0 1 I/O APIC structure<br />

Length 1 1 12<br />

I/O APIC ID 1 2 The I/O APIC’s ID.<br />

Reserved 1 3 0<br />

I/O APIC Address 4 4 The 32-bit physical address to access this I/O APIC. Each I/O APIC<br />

resides at a unique address.<br />

Global System<br />

Interrupt Base<br />

4 8 The global system interrupt number where this I/O APIC’s interrupt<br />

inputs start. The number of interrupt inputs is determined by the I/O<br />

APIC’s Max Redir Entry register.<br />

5.2.12.4 Platforms with APIC <strong>and</strong> Dual 8259 Support<br />

Systems that support both APIC <strong>and</strong> dual 8259 interrupt models must map global system interrupts<br />

0-15 to the 8259 IRQs 0-15, except where Interrupt Source Overrides are provided (see<br />

Section 5.2.12.5, “Interrupt Source Override Structure” below). This means that I/O APIC interrupt<br />

inputs 0-15 must be mapped to global system interrupts 0-15 <strong>and</strong> have identical sources as the 8259<br />

IRQs 0-15 unless overrides are used. This allows a platform to support OSPM implementations that<br />

use the APIC model as well as OSPM implementations that use the 8259 model (OSPM will only<br />

use one model; it will not mix models).<br />

When OSPM supports the 8259 model, it will assume that all interrupt descriptors reporting global<br />

system interrupts 0-15 correspond to 8259 IRQs. In the 8259 model all global system interrupts<br />

greater than 15 are ignored. If OSPM implements APIC support, it will enable the APIC as described<br />

by the APIC specification <strong>and</strong> will use all reported global system interrupts that fall within the limits<br />

of the interrupt inputs defined by the I/O APIC structures. For more information on hardware<br />

resource configuration see Section 6, “<strong>Configuration</strong>.”<br />

5.2.12.5 Interrupt Source Override Structure<br />

Interrupt Source Overrides are necessary to describe variances between the IA-PC st<strong>and</strong>ard dual<br />

8259 interrupt definition <strong>and</strong> the platform’s implementation.<br />

Version 6.0 141

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!