Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
FACP - Flag
Bit
Length
Bit
Offset
Description
SLP_BUTTON 1 5 A zero indicates the sleep button is handled as a fixed feature
programming model; a one indicates the sleep button is
handled as a control method device.
If the system does not have a sleep button, this value would
be “1” and no sleep button device would be present.
Independent of the value of this field, the presence of a sleep
button device in the namespace indicates to OSPM that the
sleep button is handled as a control method device.
FIX_RTC 1 6 A zero indicates the RTC wake status is supported in fixed
register space; a one indicates the RTC wake status is not
supported in fixed register space.
RTC_S4 1 7 Indicates whether the RTC alarm function can wake the
system from the S4 state. The RTC must be able to wake the
system from an S1, S2, or S3 sleep state. The RTC alarm can
optionally support waking the system from the S4 state, as
indicated by this value.
TMR_VAL_EXT 1 8 A zero indicates TMR_VAL is implemented as a 24-bit value.
A one indicates TMR_VAL is implemented as a 32-bit value.
The TMR_STS bit is set when the most significant bit of the
TMR_VAL toggles.
DCK_CAP 1 9 A zero indicates that the system cannot support docking. A
one indicates that the system can support docking. Notice
that this flag does not indicate whether or not a docking
station is currently present; it only indicates that the system is
capable of docking.
RESET_REG_SUP 1 10 If set, indicates the system supports system reset via the
FADT RESET_REG as described in Section 4.8.3.6, “Reset
Register.”
SEALED_CASE 1 11 System Type Attribute. If set indicates that the system has no
internal expansion capabilities and the case is sealed.
HEADLESS 1 12 System Type Attribute. If set indicates the system cannot
detect the monitor or keyboard / mouse devices.
CPU_SW_SLP 1 13 If set, indicates to OSPM that a processor native instruction
must be executed after writing the SLP_TYPx register.
PCI_EXP_WAK 1 14 If set, indicates the platform supports the
PCIEXP_WAKE_STS bit in the PM1 Status register and the
PCIEXP_WAKE_EN bit in the PM1 Enable register. This bit
must be set on platforms containing chipsets that implement
PCI Express.
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