Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
by the GPE0_BLK and GPE1_BLK register blocks, and the generic hardware registers can be in any
of the defined ACPI address spaces. A device’s generic hardware programming model is described
through an associated object in the ACPI Namespace, which specifies the bit’s function, location,
address space, and address location.
The programming model for devices is normally broken into status and control functions. Status bits
are used to generate an event that allows OSPM to call a control method associated with the pending
status bit. The called control method can then control the hardware by manipulating the hardware
control bits or by investigating child status bits and calling their respective control methods. ACPI
requires that the top level “parent” event status and enable bits reside in either the GPE0_STS or
GPE1_STS registers, and “child” event status bits can reside in generic address space.
The example below illustrates some of these concepts. The top diagram shows how the logic is
partitioned into two chips: a chipset and an embedded controller.
• The chipset contains the interrupt logic, performs the power button (which is part of the fixed
register space, and is not discussed here), the lid switch (used in portables to indicate when the
clam shell lid is open or closed), and the RI# function (which can be used to wake a sleeping
system).
• The embedded controller chip is used to perform the AC power detect and dock/undock event
logic. Additionally, the embedded controller supports some system management functions using
an OS-transparent interrupt in the embedded controller (represented by the EXTSMI# signal).
94 April, 2015 Version 6.0