Advanced Configuration and Power Interface Specification

ACPI Hardware Specification
4.8.3.5 Processor Register Block (P_BLK)
This optional register block is used to control each processor in the system. There is one unique
processor register block per processor in the system. For more information about controlling
processors and control methods that can be used to control processors, see Section 8, “Processor
Configuration and Control.” This register block is DWORD aligned and the context of this register
block is not maintained across S3 or S4 sleeping states, or the S5 soft-off state.
4.8.3.5.1 Processor Control (P_CNT): 32
Register Location: Either :
System I/O Space
or specified by _PTC Object: System I/O, System Memory, or
Functional Fixed Hardware Space
Default Value: 00h
Attribute:
Read/Write
Size:
32 bits
This register is accessed as a DWORD. The CLK_VAL field is where the duty setting of the
throttling hardware is programmed as described by the DUTY_WIDTH and DUTY_OFFSET values
in the FADT. Software treats all other CLK_VAL bits as ignored (those not used by the duty setting
value).
Table 4-21 Processor Control Register Bits
Bit Name Description
3:0 CLK_VAL Possible locations for the clock throttling value.
4 THT_EN This bit enables clock throttling of the clock as set in the CLK_VAL field. THT_EN bit
must be reset LOW when changing the CLK_VAL field (changing the duty setting).
31:5 CLK_VAL Possible locations for the clock throttling value.
4.8.3.5.2 Processor LVL2 Register (P_LVL2): 8
Register Location: Either + 4:
or specified by _CST Object:
Default Value:
Attribute:
Size:
00h
Read-Only
8 bits
This register is accessed as a byte.
Table 4-22 Processor LVL2 Register Bits
System I/O Space
System I/O, System Memory, or
Functional Fixed Hardware Space
Bit Name Description
7:0 P_LVL2 Reads to this register return all zeros; writes to this register have no effect. Reads to
this register also generate an “enter a C2 power state” to the clock control logic.
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