Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
4.8.3.3 Power Management Timer (PM_TMR)
Register Location:
Default Value: 00h
Attribute:
Read-Only
Size:
32 bits
System I/O or Memory Space
This optional read-only register returns the current value of the power management timer (PM timer)
if it is implemented on the platform. The FADT has a flag called TMR_VAL_EXT that an OEM sets
to indicate a 32-bit PM timer or reset to indicate a 24-bit PM timer. When the last bit of the timer
toggles the TMR_STS bit is set. This register is accessed as 32 bits.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates
that the feature is not supported as a fixed hardware feature, then software treats these bits as
ignored.
Table 4-19 PM Timer Bits
Bit Name Description
23:0 TMR_VAL This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off a 3.579545-MHz clock and counts while in
the S0 working system state. The starting value of the timer is undefined, thus
allowing the timer to be reset (or not) by any transition to the S0 state from any
other state. The timer is reset (to any initial value), and then continues counting
until the system’s 14.31818 MHz clock is stopped upon entering its Sx state. If the
clock is restarted without a reset, then the counter will continue counting from
where it stopped.
31:24 E_TMR_VAL This read-only field returns the upper eight bits of a 32-bit power management
timer. If the hardware supports a 32-bit timer, then this field will return the upper
eight bits; if the hardware supports a 24-bit timer then this field returns all zeros.
4.8.3.4 PM2 Control (PM2_CNT)
Register Location: System I/O, System Memory, or Functional
Default Value:
Attribute:
Size:
Fixed Hardware Space
00h
Read/Write
PM2_CNT_LEN
This register block is naturally aligned and accessed based on its length. For ACPI 1.0 this register is
byte aligned and accessed as a byte.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates
that the feature is not supported as a fixed hardware feature, then software treats these bits as
ignored.
Table 4-20 PM2 Control Register Bits
Bit Name Description
0 ARB_DIS This bit is used to enable and disable the system arbiter. When this bit is CLEAR
the system arbiter is enabled and the arbiter can grant the bus to other bus
masters. When this bit is SET the system arbiter is disabled and the default CPU
has ownership of the system.
OSPM clears this bit when using the C0, C1 and C2 power states.
>0 Reserved Reserved
90 April, 2015 Version 6.0