Advanced Configuration and Power Interface Specification

ACPI Hardware Specification
• OSPM does an OUT to the SMI_CMD port with the data in the ACPI_DISABLE field of the
FADT.
• OSPM polls the SCI_EN bit until it is sampled as RESET.
Platforms that only support ACPI always return a 1 for the SCI_EN bit. In this case OSPM skips the
Legacy to ACPI transition stated above.
4.8.2.6 Processor Control
The ACPI specification defines several processor controls including power state control, throttling
control, and performance state control. See Section 8, “Processor Configuration and Control,” for a
complete description of the processor controls.
4.8.3 Fixed Hardware Registers
The fixed hardware registers are manipulated directly by OSPM. The following sections describe
fixed hardware features under the programming model. OSPM owns all the fixed hardware resource
registers; these registers cannot be manipulated by AML code. Registers are accessed with any
width up to its register width (byte granular).
4.8.3.1 PM1 Event Grouping
The PM1 Event Grouping has a set of bits that can be distributed between two different register
blocks. This allows these registers to be partitioned between two chips, or all placed in a single chip.
Although the bits can be split between the two register blocks (each register block has a unique
pointer within the FADT), the bit positions are maintained. The register block with unimplemented
bits (that is, those implemented in the other register block) always returns zeros, and writes have no
side effects.
4.8.3.1.1 PM1 Status Registers
Register Location: System I/O or Memory Space
Default Value: 00h
Attribute:
Read/Write
Size: PM1_EVT_LEN / 2
The PM1 status registers contain the fixed hardware feature status bits. The bits can be split between
two registers: PM1a_STS or PM1b_STS. Each register grouping can be at a different 32-bit aligned
address and is pointed to by the PM1a_EVT_BLK or PM1b_EVT_BLK. The values for these
pointers to the register space are found in the FADT. Accesses to the PM1 status registers are done
through byte or word accesses.
For ACPI/legacy systems, when transitioning from the legacy to the G0 working state this register is
cleared by BIOS prior to setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only
platforms (where SCI_EN is always set), when transitioning from either the mechanical off (G3) or
soft-off state to the G0 working state this register is cleared prior to entering the G0 working state.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates
that the feature is not supported as a fixed hardware feature, then software treats these bits as
ignored.
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