Advanced Configuration and Power Interface Specification

ACPI Hardware Specification
4.8.2.3 Sleeping/Wake Control
The sleeping/wake logic consists of logic that will sequence the system into the defined low-power
hardware sleeping state (S1-S4) or soft-off state (S5) and will wake the system back to the working
state upon a wake event. Notice that the S4BIOS state is entered in a different manner (for more
information, see Section 16.1.4.2, “The S4BIOS Transition”).
SLP_EN
PM1x_CNT.S4.13
SLP_TYP:3
PM1x_CNT.S4.[10-12]
"OR" or all
Wake
Events
PWRBTN_OR
Wakeup/
Sleep
Logic
Sleeping
WAK_STS
PM1x_STS.S0.15
Figure 4-18 Sleeping/Wake Logic
The logic is controlled via two bit fields: Sleep Enable (SLP_EN) and Sleep Type (SLP_TYPx). The
type of sleep or soft-off state desired is programmed into the SLP_TYPx field and upon assertion of
the SLP_EN the hardware will sequence the system into the defined sleeping state. OSPM gets
values for the SLP_TYPx field from the \_Sx objects defined in the static definition block. If the
object is missing OSPM assumes the hardware does not support that sleeping state. Prior to entering
the desired sleeping state, OSPM will read the designated \_Sx object and place this value in the
SLP_TYP field.
Additionally ACPI defines a fail-safe Off protocol called the “power button override,” which allows
the user to initiate an Off sequence in the case where the system software is no longer able to recover
the system (the system has hung). ACPI defines that this sequence be initiated by the user pressing
the power button for over 4 seconds, at which point the hardware unconditionally sequences the
system to the Off state. This logic is represented by the PWRBTN_OR signal coming into the sleep
logic.
While in any of the sleeping states (G1), an enabled “Wake” event will cause the hardware to
sequence the system back to the working state (G0). The “Wake Status” bit (WAK_STS) is provided
for OSPM to “spin-on” after setting the SLP_EN/SLP_TYP bit fields. When waking from the S1
sleeping state, execution control is passed backed to OSPM immediately, whereas when waking
from the S2-S4 states execution control is passed to the BIOS software (execution begins at the
CPU’s reset vector). The WAK_STS bit provides a mechanism to separate OSPM’s sleeping and
waking code during an S1 sequence. When the hardware has sequenced the system into the sleeping
state (defined here as the processor is no longer able to execute instructions), any enabled wake
event is allowed to set the WAK_STS bit and sequence the system back on (to the G0 state). If the
system does not support the S1 sleeping state, the WAK_STS bit can always return zero.
-If more than a single sleeping state is supported, then the sleeping/wake logic is required to be able
to dynamically sequence between the different sleeping states. This is accomplished by waking the
system; OSPM programs the new sleep state into the SLP_TYP field, and then sets the SLP_EN bit–
placing the system again in the sleeping state.
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