Advanced Configuration and Power Interface Specification

ACPI Hardware Specification
Register Block A
Register Block B
Bit e
Bit d
Bit c
Bit b
Bit a
Register
Grouping
Figure 4-13 Example Fixed Hardware Feature Register Grouping
As an example, the above diagram represents a register grouping consisting of register block A and
register block b. Bits “a” and “d” are implemented in register block B and register block A returns a
zero for these bit positions. Bits “b”, “c” and “e” are implemented in register block A and register
block B returns a zero for these bit positions. All reserved or ignored bits return their defined ACPI
values.
When accessing this register grouping, OSPM must read register block a, followed by reading
register block b. OSPM then does a logical OR of the two registers and then operates on the results.
When writing to this register grouping, OSPM will write the desired value to register group A
followed by writing the same value to register group B.
ACPI defines the following fixed hardware register blocks. Each register block gets a separate
pointer from the FADT. These addresses are set by the OEM as static resources, so they are never
changed—OSPM cannot re-map ACPI resources. The following register blocks are defined:
Registers
PM1a_STS
PM1a_EN
PM1b_STS
PM1b_EN
PM1a_CNT
PM1b_CNT
Register Blocks
PM1a_EVT_BLK
PM1b_EVT_BLK
PM1a_CNT_BLK
PM1b_CNT_BLK
Register Groupings
PM1 EVT Grouping
PM1 CNT Grouping
PM2_CNT
PM2_CNT_BLK
PM2 Control Block
PM_TMR
P_CNT
P_LVL2
P_LVL3
GPE0_STS
GPE0_EN
GPE1_STS
GPE1_EN
PM_TMR_BLK
P_BLK
GPE0_BLK
GPE1_BLK
PM Timer Block
Processor Block
General Purpose Event 0
Block
General Purpose Event 1
Block
Figure 4-14 Register Blocks versus Register Groupings
The PM1 EVT grouping consists of the PM1a_EVT and PM1b_EVT register blocks, which contain
the fixed hardware feature event bits. Each event register block (if implemented) contains two
registers: a status register and an enable register. Each register grouping has a defined bit position
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