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Stop with boring presentations!,
Long before there were computers
there were bad presentations. And
there still are. All of you attending
presentations regularly experience
this by suffering boring hours
where conference speakers fail to
use your time and theirs wisely.
Most of the presentations are too
detailed for the audience, use visuals
that are far too complex, and
generally show a lack of passion
from the orator.
When you think of technical pre-
Michael Moesslang
sentations, you may think of dark
rooms, masses of slides, and a
voice at the front of the room narrating in detail the facts for the audience.
However, there are definitely exceptions and ways to deliver
a speech that manage to reach the goal content-wise and at the
same time persuade and entertain the audience. The worst belief is
that your presentation has to be like presentations have always been
in your company, as that is the standard. Being standard - another
word is mediocre - never leads to being convincing. And isn’t this
what it is all about? To really convince your audience? Lots of technicians
think they are not in sales and therefore they do not need to
be convincing. So very wrong! To convince an audience is selling observations,
conclusions, and projections. That also is sales, isn’t it?
To reach your audience and have it leave satisfied and impressed after
your presentation, you’d better think about breaking several of these
standard patterns and relate to some of the rules of human communication.
One of these is to speak in a clear and understandable
way with as few technical abbreviations or terms as possible. Never
assume that your audience has the same level of technical knowledge
as yourself. Slides filled with masses of text in small fonts do not support
but rather destroy the impact of your words. Visuals are far better
and should clearly show what you wish to point out. Never forget
that your audience will see the visual - maybe a technical illustration
or a spreadsheet - for the very first time. They will need time
to understand and are not able to listen to you during that process.
People cannot read and listen at the same time. To get and keep an
alert audience you should speak with suspense and use loops. A loop
is a teasing announcement creating suspense. In the following the audience
will wait curiously for the later clarification of facts and therefore
stay with you.
If you are going to get up in front of your audience and say that the
design of your strategy matters, that the design of your software or
hardware matters, that your content matters, then at the very least the
structure and visuals you use also need to be the result of credible design.
Then, and only then, can you give presentations that are better
than the rest out there. And win over your audience.
Yours sincerely,
Michael Moesslang
VIEWPOINT
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3 November 2009
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CONTENTS
Viewpoint 3
Cover Story
High performance semiconductors
paved the way for electric bicycles 6
Industrial Control
Making industrial systems safer
by meeting the IEC 60730 standards 9
Tools & Software
Design kits for PCBs featuring
embedded Atom processors 12
Rapid prototyping using software
configuration management 14
Tools & Software
Different design patterns for
integrating Simulink with Stateflow 18
Micros & DSPs
Single-chip coherent multiprocessing
boosts embedded performance 20
Accelerating early stages of the design
cycle with i.MX processors 24
FPGAs, PLDs & ASICs
The drive to lower power opens up
new FPGA applications 26
Flexible power system management
capabilities for embedded systems 29
Low-power FPGA solutions for
graphics applications featuring LCDs 31
Highly configurable embedded 32-bit
RISC processor for FPGA applications 33
Product News 36
Cover Photo
Infineon Technologies
November 2009 4
High performance semiconductors
paved the way for electric bicycles PAGE 6
This article describes the technical progress in electronics and
power electronics which enables nowadays e-bikes as mass products
for green personal transportation.
Making industrial systems safer
by meeting the IEC 60730 standards PAGE 9
This article discusses the different classes of the IEC 60730 standards
for appliances and industrial control and shows how MCU
manufacturers can help by delivering hardware features, such as
independent watchdogs, CRC engines, ECC and software periodic
test routines to gain IEC 60730 compliance.
Rapid prototyping using software
configuration management PAGE 14
Software configuration management
contributes powerfully to
rapid prototyping of both hardware
and software for embedded
systems, especially with the communication
problems arising from
far-flung design teams and -
system architects. This article describes latest techniques such as
lazy copying and reverse delta archiving.
Single-chip coherent multiprocessing
boosts embedded performance PAGE 20
This article explains how the MIPS32 1004K coherent processing
system brings together MIPS multi-threading and coherent SMP
in a single IP block to provide scalable, high-density embedded
computing power.
The drive to lower power opens up
new FPGA applications PAGE 26
Power is often a more important
design consideration today than
performance. Portable, powerconscious
electronics demands
low-power components of every
kind, a demand increasingly met
by FPGAs. This article highlights
the trend and technology by
examples drawn from many fields.
Flexible power system management
capabilities for embedded systems PAGE 29
This article shows how programmable
logic devices are well suited
to enable flexible and efficient
power management functions,
especially for battery-powered
embedded systems.

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internationally. All other trademarks are the property of their respective owners.

COVER STORY
High performance semiconductors
paved the way for electric bicycles
By Juergen Hoika, Infineon Technologies
November 2009
This article describes
the technical progress
in electronics and power
electronics which enables
nowadays e-bikes as mass
products for green personal
transportation.
■ Electrical drives are not new in transport:
Trams and trains have been running on electricity
for a long time. Electrically driven vehicles
have been around since the 1830s and more
than 100 years have now passed since the invention
of the electric bicycle. In 1895, Ogden
Bolton, Jr. applied for the first patent for a battery-operated
bicycle with a 6-pole brush
motor built into the rear wheel. Development
and commercialization of the electric bicycle
have come a long way in those 110 years. From
a technological point of view, the breakthrough
undoubtedly came with the availability of
long-lived accumulators - such as the lithiumpolymer
battery - and with the increase in the
power and efficiency of electric motors brought
about by the use of electronics. Electric bikes are
part of a wide range of Light Electric Vehicles
(LEVs). Generally designed for one person and
small cargo capacity, electric bike range, speed,
and costs are moderate, providing clean, quiet,
convenient and efficient local transportation.
What is that market? Worldwide, bicycles and
scooters are the number one mode of transportation.
An estimated one billion bicycles are
in daily use, and more than 100 million new bicycles
enter the world market each year. China,
for example, has 34 bicycles per 100 inhabitants
and has a market for more than 30 million bicycles
annually. So it is no surprise, that the
commercialization of the electric bicycle has
been driven mainly by its introduction and subsidization
in China. The production figure of
only 40,000 electric bicycles in China in 1998
rose to 10 million within 7 years. By 2008 this
figure had almost doubled. What caused this
breakthrough for the electric bicycle in China?
These conveyances became the favorite means
of transport for the Chinese populace because
they offer a cheap, convenient form of personal
mobility as an attractive alternative to public
transport and the push-bike. In China,
electric bicycles are subsidized by national and
many local governments, thanks to their low
energy consumption and freedom from emission
– a particularly important aspect in
China`s overloaded urban areas. They have already-
quite literally - overtaken the conventional
bicycle in some cities.
In Europe, the electric bicycle suffered from a
negative image for many years. It was heavy, and
was regarded as un-sportsmanlike, and found a
place more as an aid than as a means of transport
in its own right. In view of the stream of
announcements of new, so-called “Pedelecs”
(Pedal Electric Cycles), these times seem to be
over at last. Cities in Europe are also beginning
to invest in this means of transport. In Switzerland,
too, the Elektrovelo is booming, thanks to
the NewRide subsidization programme; in Austria,
the Klima:aktiv-Programme subsidizes the
purchase of a Pedelec to the tune of up to € 400,
6
Figure 1. Using the benefits of
high performance semiconductors
electric bicycles provide
clean, quiet, convenient and
efficient local transportation
and in numerous German cities, such as
Stuttgart and Kaiserslautern, new mobility concepts
involving electric bicycles are being
launched. New business concepts are emerging.
Personal mobility is becoming a service, analogous
to mobile communications. Companies
such as Movelo rent out Pedelecs, and also offer
battery exchange in interesting holiday resorts
and urban areas. This way, users pay for mobility
as required, and do not have to worry about
servicing, such as battery maintenance. Electric
bicycles have also been in service in a commercial
environment for years; in many countries,
mail is already being delivered by Pedelec.
The technical breakthrough for electric bicycles
came with the use of electronics. These control
electric motors efficiently, thus optimizing
performance and battery life. The most frequently
used topography in series production
of electric bicycles today is a brushless DC
motor (BLDC) with Hall sensors. A basic electric
bicycle runs on a BLDC motor, is powered
by batteries and controlled from an ECU (Embedded
Control Unit). The BLDC motor for the
electric bicycle is of the standard three phase
trapezoidal type, typically rated at a few hundred
watts and the battery voltage is usually
36V or 48V. Almost all the electronics in the
electric bicycle are found in the ECU, it contains
the inverter circuit for the motor; temperature
sensor; fault detection; SMPS; analogue and dig-

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COVER STORY
Figure 2. Market forecast for electric bicycles in China, iSuppli, June 2009
Figure 3. Block diagram of a BLDC motor control in a Pedelec
ital I/Os; and finally the controller itself. Some
ECUs have advanced features such as remote
controlled alarm and electric horn as well. All of
these as well as the wiring are usually packed
into a robust and very compact metal box.
Infineon is the leading company in the area of
semiconductors for electric bicycles. In about
every second electric bicycle worldwide, the
motor is controlled by an 8-bit microcontroller
of Infineon XC800 family. One reason for this
is that the product characteristics are tailormade
for this application at low cost. The special
functions in the microcontroller (fast
ADC, Capture/Compare unit, etc.) make for
particularly fast signal recognition and signal
generation to switch the individual phase currents
of the motor. The cyclist notices this by
the excellent performance of the electric bicycle
in every load state. Another reason is high
quality and reliability as products are build on
automotive proven technologies.
Figure 4. Reference design of the control unit
Further essential elements of the motor
electronics are the robust, intelligent power
semiconductors. The Infineon EiceDRIVER
portfolio includes full-bridge drivers to control
power devices such as IGBTs or MOS transistors
in 3-phase systems with a blocking voltage
of up to 600V. Based on Silicon-On-Insulator
(SOI) technology, these devices are very resistant
to negative transient voltages. Unlike standard
monolithic high-voltage IC technology,
Infineon SOI thin-film technology does not
have parasitic thyristor structures. The result is
outstanding robustness against latch-up when
exposed to extreme temperature and voltage
conditions. Furthermore, they switch off
automatically in many error modes to prevent
destruction of the electronics or the motor.
The e-bike is one example of the broad range of
applications which benefits from the unique
features of the OptiMOS2 or OptiMOS3 power
MOSFETs, offering a combination of the lowest
available on-state resistance in comparable
packages and lowest gate drive requirements.
These MOSFETs feature excellent switching
performance, they help to increase power density
in the application and consequently they
save energy. In addition these MOSFETs provide
the highest immunity to dynamic turn-on.
Hall sensors from Infineon, such as the
TLE4946, were developed specifically for motor
control applications, and are characterized in
November 2009 8
the electric bicycle by their precision and immunity
to interference signals. Infineon have
been offering solutions for electronics in electric
bicycles for over three years now. Meanwhile
there is a second generation of a reference
system available, that comprises both the reference
circuit with all active and passive components,
and a reference platform for software
development. The software library for electric
bicycles includes functions such as evaluation of
input units, battery voltage monitoring, and
measurement of phase currents.
On the electronics side, the semiconductor
components will provide designers with sufficient
computing performance, increased switching
efficiency, and more safety and diagnosis
functionstocreateanewclassofelectricbicycles.
The 8-bit XC800 microcontroller series offers
derivatives with a vector computer, which
allows implementation of Field Oriented
Control (FOC) for the price of a standard 8-bit
microcontroller. Thanks to FOC, non-sensor
topologies in the electric drives of the Pedelecs
are possible, and the efficiency of the motor is
further increased. If even more processor
performance needed in motor scooters and
motorcycles, Infineon offers the 16-bit microcontroller
series XE166 with the same peripheral
functions, for example signal generation
(Capture Compare Unit), as in the XC800 series.
This creates a scalable development platform.
The mentioned reference system is under
continuous further development, in order to
shorten the development times for the motor
control unit with the help of more software
functions. In addition to this, Infineon offers
the auto-code generator DAvE Drive, which
generates, with just a few mouse-clicks, blockcommutation
or FOC code that is optimized to
the microcontroller architecture.
Electric drives for bicycles know no limits. The
next generation in the upper performance
range is going into mass production: the socalled
E-Scooter. The electric motor has also
found its way into the motor-cycling world. The
12th of June 2009 saw the first “Zero Emission
Motorcycle Race”. The winner was Chris Heath
on a Native TTGXP, which reached 160km/h on
the legendary Isle of Man circuit. New business
models, like the renting of electric bicycles in
urban areas and holiday resorts, will certainly
remove any obstacles in the run-up to Pedelec
mobility with regard to the charging and maintenance
of batteries. It will be exciting to see
what interesting kinds of electric-powered
bicycle will come on the market in the coming
months and years, and what concepts cities and
towns will offer consumers with regard to
personal mobility with Pedelecs. The technological
prerequisites to support the next generations
of e-bikes are all already in place. ■

Making industrial systems safer
by meeting the IEC 60730 standards
By Dugald Campbell, Freescale
This article discusses the different
classes of the IEC 60730 standards
for appliances and industrial control
and shows how MCU manufacturers
can help by delivering hardware features,
such as independent
watchdogs, CRC engines, ECC and
software periodic test routines to
gain IEC 60730 compliance.
■ With the introduction of the International
Electrotechnical Commission IEC 60730 standards
series, household appliance and industrial
control manufacturers now have to consider introducing
new design enhancements to their
automatic electronic controls that ensure their
components’ safe and reliable operation. IEC
60730 standards series on automatic electrical
controls for household and similar use, Part 1,
is one of many standards used by large appliance
manufacturers. IEC 60730 is also referenced
by other standards for other systems,
such as boiler ignition systems (EN 297) and
medical electrical equipment (IEC 60601), that
cover general requirements for basic safety and
essential performance.
IEC 60730 discusses mechanical, electrical,
electronic, environmental, endurance, EMC
and abnormal operation of AC appliances. IEC
60730 Annex H: Requirements for Electronic
Controls, specifically relates to microcontrollers
(MCUs), detailing new test and diagnostic
methods to ensure the safety of embedded control
hardware and software for automatic systems.
Its focus is to provide measures to ensure
that the embedded software design functions
safely and reliably if a fault condition occurs
within the system sub-components, such as
CPU, memory, interrupts, program counter,
communication interfaces and software
program flow.
Today the majority of automatic electronic controls
use single-chip MCUs (microprocessors
with embedded memory and input/output
peripherals). Manufacturers develop real-time
embedded software that executes within the
MCU and provides the hidden intelligence that
controls an electro-mechanical device. Measures
detailed in IEC 60730 are critical to help
ensure that such an electro-mechanical device
INDUSTRIAL CONTROL
will not be hazardous to users. IEC 60730/EN
60335 segments automatic control products
into three different classifications. Class A: not
intended to be relied upon for the safety of the
equipment, Class B: to prevent unsafe operation
of the controlled equipment. Class C: to prevent
special hazards.
Class A controls are deemed not hazardous if
the software malfunctions, and thus IEC 60730
does not require the manufacturer to implement
system checks. A class B system likely has
automatic controls where a possible hazard
could occur and result in harm to a human
being. Generally, the controls are characterized
by how the class B system is implemented and
if the critical safety system features some form
of redundancy (in hardware and/or software).
If the automatic control relies on a specific safety
function and there is no redundancy, then
the system will likely be deemed class C. If the
9 November 2009

INDUSTRIAL CONTROL
automatic controls directly control an explosive
substance, such as gasoline, the system will be
deemed class C. The various components of an
embedded system that must be tested are summarized
in Table H.11.12.7. of IEC 60730
Annex H. For each of the listed class B and class
C components, optional measures are given for
the manufacturer to deploy within the automatic
system. Table 1 summarizes the required
components that need to be tested and monitored
to ensure the system meets class B specifications.
CPU registers can be monitored by
using a periodic test routine that writes a 0xAA
pattern followed by a 0x55 pattern to verify no
register bits are stuck at a 1 or 0 state. A CPU
program counter can be similarly tested with a
0x55/0xAA pattern by placing small routines at
addresses 0x5555.. and 0xAAA.. that have return
from subroutine instructions (RTS). The CPU
should execute these routines and then examine
the contents in the stack pointer.
Interrupt handling and execution is verified by
a method called independent time base monitoring.
This requires a regular periodic check
from a time base independent of the CPU
clock. An example is having a real-time interrupt
clocked by an independent 1 kHz oscillator
that includes a check on token counters of
all interrupts utilized. If any irregularity is discovered,
then the CPU is forced into a routine
that places the application in a safe state. The
clock or the CPU clock is also required to be
checked by an independent time-base monitor.
An independent clocked timer, such as a realtime
interrupt, can be used to make timestamps
at regular intervals from a CPU clocked timer.
Additionally, Freescale MCUs feature a watchdog
counter that is clocked by an independent
timebase. This feature provides an additional
check if the CPU clock stops, ensuring that an
asynchronous reset occurs to place the system
November 2009
in a safe state. Watchdogs that are clocked from
the same source as the CPU cannot provide this
protection. For invariable memory (flash), the
manufacturer is required to check for single bit
faults, which can be performed using a modified
checksum routine. The main issue here is
that there is no common method or routine for
deploying a modified checksum. Manufacturers
have taken the approach of deploying the
program memory cycle redundancy checking
(CRC) signatures because it is well understood
and has a reliable mechanism for identifying
single-bit errors. After all bytes have been read,
each byte is run through a CRC calculation.
Once that calculation is made, it can be compared
to a so-named golden CRC signature to
verify no single faults exist. Freescale has created
a hardware CRC engine that will provide a
fast method of creating a 16-bit CRC.
For small memory footprints, the CRC can be
calculated in software within a reasonable time
frame. Variable memory (RAM) can be verified
as having no DC faults by executing a periodic
test using the well-known March C or March X
test pattern. These March patterns require a lot
of execution time for most embedded systems,
and the designer must segment the RAM into favorable
sizes, checking each segment in sequence.
Freescale has developed March C and
March X tests for HCS08 and MC56F80xx controllers,
which can help speed up the development
of a class B system. The March X pattern is
a subset of March C where only steps 1, 2, 5 and
6 are executed, thus saving CPU execution time.
Components 4.3 addressing, 5.0 internal data
path and 5.2 addressing (table 1) are covered by
implementing the above variable and invariable
periodic test routines. 6.0 external communication
refers to protocols that are used to interface
with components external to the automatic
control system, such as UART communication
between a control board and a motor
control board. There are several optional measures
to ensure reliable communication, such as
adding a 16-bit CRC to data transferred via the
10
communication port and transfer redundancy,
which is simply sending data twice. A timing
component, as in the wrong point in time, and
sequence of external data exchanges can be reliably
checked using independent time slot
monitoring, the same as used for interrupts.
Components 7.0 periphery, 7.2.1 analog I/O
and 7.2.2 analog multiplexers (table 1) require
the manufacturer to carry out plausibility
checks prior to application use. These employ
a number of techniques, including making
upper/lower limits on ADC inputs, redundant
ADC inputs to check multiplexer, and short circuit
and open circuit tests of adjacent pins to a
safety-critical signal line. Subjecting a system
design to all the measures described will provide
IEC 60730 Class B compliance.
Table 2 summarizes the required components
that need to be tested and monitored to ensure
the system meets class C specifications. For class
C systems there is one additional component
that needs to be tested and more stringent
measures placed on four of the existing components.
The additional component is 1.2
CPU instruction decoding and execution,
which is required to check that the CPU is decoding
the instructions used to perform the
safety feature. Table H.11.12.7 of IEC 60730
Annex H provides three optional measures to
test for this component: Dual CPU implementation
with comparison, internal hardware detection,
and periodic self-test using equivalence
class test.
Freescale Power Architecture products, such as
the MPC5510 family, have dual CPU cores that
can execute simultaneously, and the execution
results can be compared prior to executing a
safety function. Internal hardware detection
through error code correction (ECC) is provided,
which uses a form of parity when reading
program instructions and can automatically
correct single parity errors. This feature can be
found on S12X family members, such as the
MC9S12XE100, as well as the MPC5510 fami-

Table 1. Class B components that need testing
and monitoring
ly, which has ECC on both flash and RAM
memory. For 8-bit S08 CPU, a CPU instruction
test is developed that can be executed prior to
running power-up on the end application.
This test routine requires approximately 2
Kbytes of program memory, but it is modular,
which allows removing tests for instructions
that are not utilized by the safety application.
Execution time for the full test is 3666 CPU
BUS cycles (183.3 s at 20MHz). TÜV SÜD has
validated and certified this test routine to be
IEC 60730-compliant, and the test routine is
available for Freescale customers. In addition to
the extra component to be tested, there are four
components of class C systems that require
more stringent testing: CPU register test, variable
memory (RAM), invariable memory
(flash), and external communications.
CPU register test requires the manufacturer to
check for DC faults on the CPU registers, which
can be accomplished using a walking 1s and
walking 0s pattern. The last figure in this article
shows a walking 1s pattern on an 8-bit register.
By executing this pattern and confirming
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Table 2. Class C components that need testing
and monitoring
the data at each step, all DC faults will be exposed.
A walking 0s pattern is similar to the
walking 1s pattern with all data inverted, and it
should also be performed. Variable memory
(RAM) testing requires the same techniques as
used for the CPU register (walking 1s and walking
0s to check for DC faults). For RAM arrays
of >2 Kbtes, executing such a test can be time
consuming. However, the manufacturer can
split the RAM array into small segments (32 to
128 bytes), and each RAM segment can be tested
in sequence while executing the application.
Note that the manufacturer will likely need to
pause the application while it tests each application
and disable interrupts to ensure no program
variables are inadvertently corrupted.
Freescale has developed a walking 1s and walking
0s RAM test for the HC9S08AC60 MCU,
which segments the RAM into 48-byte segments.
This is modular software, however, and
can be easily modified to support larger or
smaller RAM arrays. Invariable memory (flash)
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11
INDUSTRIAL CONTROL
for class C systems requires the user to look for
99.6 percent coverage of all bits. This can be covered
by ECC or by a 32-bit CRC. Optionally, redundant
memory can be deployed where the
CPU can periodically check that both arrays
compare. For external communications components
meeting class C specifications, the
manufacturer is required to implement either a
32-bitCRCtodatatransfersordeploydataredundancy,
where the data is sent at least twice
and the redundant data is modified in some
form,suchasinvertingthesecondpieceofdata.
Another option is to use comparison or redundant
functional channels with comparison. By
using two communications ports and sending
the data on both ports, the software can compare
the received data to ensure they match.
Periodic test routines for Freescale MCUs were developed
that users can deploy in their application
code. These developed routines have each been
certified by a certification body, such as VDE or
TÜVSÜD,tomeetIEC60730requirements.■
Product News
■ Rutronik: low-power high-precision
op amps
Microchip Technology presents three new families
of low-power, high-precision operational
amplifiers broadening the portfolio of high precision
op amps with Gain Bandwidth Product
from 10kHz to 50MHz. The new products are
available at distributor Rutronik now.
News ID 450
■ Toshiba: 32nm mSATA and half-slim
SSD modules
Toshiba Electronics Europe has announced a
series of solid state drive modules using the
latest generation Toshiba 32nm MLC NAND
flash. The Toshiba SG2 modules are offered in
two types, one based on the new low-profile
mini-SATA interface standard and the other
aHalf-Slimtype,whichusesaSATAconnector.
The drives are available in 30GB and
62GB modules. Volume production will start
in October.
News ID 486
■ Fujitsu: graphics SoC with integrated
dual APIX link
Fujitsu has announced the MB86R02 ‘Jade D’,
the latest device in its ‘Jade’ SoC family,
which incorporates 32-bit ARM926EJ-S CPU
core and the company’s graphics processor
‘Coral PA’. Based on Fujitsu’s proprietary
90nm CMOS process technology, ‘Jade D’ is
optimised for automotive applications requiring
high CPU performance combined
with sophisticated 2D/3D graphics.
News ID 549
November 2009

TOOLS &SOFTWARE
Design kits for PCBs featuring
embedded Atom processors
By Dirk Mueller, FlowCAD
This article describes the
issues in PCB design associated
with the latest fast embedded
processors. Design kits
including all design rules and
a reference board are offered
by most semiconductor companies,
normally subject to
non-disclosure agreements.
■ With the new generation of embedded
processors like Intel Atom, the PCB design
process moves to another level of complexity.
The numbers of design constraints are dramatically
increased and the tolerances of these
design rules are getting tighter and tighter.
Miniaturization also adds a new dimension to
the design challenges. In the past it was possible
to build an embedded PC from scratch, but
today it is crucial to implement and reuse
proven models and reference designs from
semiconductor vendors like Intel, Xilinx, etc, in
order to reach design closure without missing
project deadlines. With today’s high performance
semiconductors, differential high speed
must not only control differential impedance
and parallelism of the two tracks, but the signals
must also be controlled in length for each track,
and match the length of all other tracks in the
same bus including control signals.
In a typical Atom design you find a memory
control hub, which is connected via the 64-bit
wide front side bus to the microcontroller. External
communication is made through a PCIexpress
interface and the DDR2 memory is
connected through a one-hundred-bit wide
memory interface to each memory component.
In embedded systems, the dimensions of a PCB
are similar to the size of a credit card. Real es-
tate on the board is limited also by the given locations
of the Com Express connector and the
mounting holes. To make the design process
really challenging the manufacturing costs
have to be low, so the number of layers available
for the designer to select from is typically reduced
to below ten.
Many semiconductor companies offer their
customers design kits under a non–disclosure
agreement. These kits include the definition of
all required design rules, and these rules are
managed in a constraint management system,
where each value for the net length, impedance
and delta[CDSI1] to the other nets in a group
are collected. To get the real value of the electrical
net, the length from the last transistor on
the CPU chip has to be measured to the first
input buffer from the [CDSI2] memory control
hub. Since the chips are not mounted directly
onto the PCB, the internal length of the signal
inside the IC has to be added to this calculation.
This value is called pin delay. This value always
existed, but the tolerances were bigger, so the internal
pin delay could be ignored to calculate
length of signals. In modern designs two things
have changed: the tolerances are reduced due to
increases in the front side bus speed i.e. 533
MHz, and the topology is made with signals
which have to be of the same length. So the pin
November 2009 12
Figure 1. Example of an
embedded module based
on Atom processor
delay can no longer be ignored and each individual
value for each pin has to be respected.
Spacing of decoupling capacitors to the Vcc and
GND pins of the IC is getting smaller if the
transmission speed is increasing. The efficient
distance for a ceramic capacitor with a low
equivalent series resistance is only several millimeters,
so the placement of these components
should remain the same as the original floor
planning of the reference design kit. In the constraint
manager this maximum spacing can be
attached to the capacitor and individual pins of
an IC, so during placement of the capacitor the
designer gets a visual feedback if the component
is placed too far away. A wrong placement
would reduce the power integrity (PI) and
destabilize the complete power delivery system,
which can result in malfunction of the module.
Memory modules like DDR2 have to be connected
to the memory hub controller. These
connections of the address and data busses have
very complex structures and detailed rules
how to connect the individual signals. Such a
structure is called topology. For one DDR2 signal,
the signal will split like a tree into different
branches. The impedance for parts of the
branch has to be different because of signal integrity
(SI) requirements. After a split the two
new branches have to be matched in length to

Figure 2. Design rules are managed in a constraint manager
Figure 3: DDR2 topology
each other. After two splits the last four branches have to be matched in
length. In a 64-bit wide data bus the length of all nets have to be matched,
consequently the total number of combined matched length rules is huge
and nearly impossible to manage manually. In Allegro PCB editor and
constraint manager the control of such a complex task is implemented
in an efficient and user-friendly way. From the design kit the requirements
for a single net are stored in the constraint manager (matching including
tolerances). In a second step the matching rules between all nets in
a bus (and groups of nets in the bus) are defined as a second hierarchy
of rules, and include also the specified tolerances. This complete rule set
for DDR2 is defined in one topology. While the definition is stored in the
constraint manager, the PCB editor will give online feedback if a value is
violating the specification. Allegro PCB editor will also display the value
of the tolerances in a visual way, so the adjustment of all matched groups
is made fast and flawless.
An Atom design kit includes a complete multi-page schematic of a tested
reference design in OrCAD capture format or alternatively in Allegro
design entry HDL. So if you start the first Atom design, you do not have
to start from scratch, but can reuse the component symbols as well as
several pages of the reference design. In the kit is also a complete layout
of a reference design made in Allegro PCB editor. With this design, you
can see how the fan-out of the Atom CPU was made and how decoupling
capacitors were placed under and around the CPU. The processor fan-out
is only one task of a design. You will also find structures for the power
delivery system, which power regulators were used and how the power
delivery system was designed to fulfil the complex demand of the CPU.
All definitions of the PCB footprint can be extracted from the reference
design and stored in the local library, which saves a lot of time. ■
TOOLS &SOFTWARE
13 November 2009

TOOLS &SOFTWARE
Rapid prototyping using software
configuration management
By Dave Robertson, Perforce Software
■ Over time, faster and better tools and processes
have steadily shortened the time-to-market
for new embedded systems. As ever more projects
involve the collaboration of increasing
numbers of different design teams and third
parties spread across the world, producing
working prototypes is becoming as much a logistical,
as a technological, challenge. New development
techniques have emerged that try to
give more control in this area. Methods such as
agile development view the entire development
process as a series of small step releases, where
the software evolves and is continuously updated.
Increasingly used by enterprise software
development teams, Agile is making some inroads
into embedded projects as it can provide
extra value to customers.
However, the sheer global scale of some embedded
systems development projects, and the
quantity and size of the data and variants involved,
takes this beyond merely a process problem.
One way these challenges can be addressed
is with software configuration management
(SCM) systems. Designed for traditional software
development, modern SCM systems can
handle large numbers of files and variants for
globally distributed engineering teams. They
also enable rapid prototyping involving multiple
sites and many hundreds of collaborating
developers. It is rare to come across a new product
that is built completely from scratch. More
November 2009
Software configuration management
contributes powerfully
to rapid prototyping of
both hardware and software
for embedded systems, especially
with the communication
problems arising from farflung
design teams and -
system architects. This article
describes latest techniques
such as lazy copying and
reverse delta archiving.
likely there is a mixture of reliable commodity
components - hardware and software - with
new proprietary IP and custom logic that cements
all the parts together. The location of the
teams and tracking the large quantity of items
involved means that pulling all the pieces together
in a timely way to produce a working
prototype or early release candidates is a major
issue.
Prototypes increasingly require the management
of many different types of file - the output
from EDA tools, hardware design schematics,
software source code and so on, along with
tracking their use and reuse. As the development
progresses, the files go through many revisions
and are combined in a range of different
configurations. The capture, organisation
and management of this complex array of information
and ensuring the right versions of
the right files are where they need to be, becomes
non-trivial. This often leads to a significant
reduction in productivity during the
prototyping stage as well as the overall development
time.
At its simplest, an SCM system tracks and manages
the digital files created in the design and
development process. Basic features of the system
include version control, change history, and
tracking the files that have been checked out of
the system for editing. The more advanced sys-
14
Figure 1. Many variants and
prototypes can be born out of
a good idea.
tems provide configuration management, the
act of recording an arbitrary collection of files
and their versions that have some special significance
to the project and may need to be recalled
or recreated at some future point. To help
with the strenuous demands of an embedded
systems development, an SCM system needs to
support rapid prototyping and distributed
development teams.
There are many contributors involved in developing
the finished hardware and software.
Software developers and hardware engineers
have already received a mention. But there are
also documentation writers and testers, too.
And, for truly integrated teams, the team may
include the web designers building the product
pages, and the marketing folks producing collateral
and so on. Their combined output involves
the need to handle the wide range of file
types that the tools of the team generate - from
graphical behavioural models, through the
VHDL for the hardware design and C text files
for the middleware and applications, to the
EDA design files for the hardware and the libraries
and compiled binary code for the software.
And not forgetting all the test and verification
files for both the hardware and software.
To be effective, the SCM system has to be both
fast and secure, but also easy to use so as to have
minimal impact on the day-to-day activities of

Figure 2. Propagating bug fixes and new features between variants is a management challenge.
Figure 3. Lazy copying uses fact that variant is identical to original to save space when branching.
users.Savingchangestofilesmustbequickand
easy, otherwise users will avoid using or pay lip
service to the system and the time and management
advantages are missed. Similarly, the
latest revisions from teams and third parties
around the world should be available as soon as
possible otherwise time is lost by having to sort
out competing revisions. All the revisions have
to be stored safely and securely with the minimum
of cost in storage space and retrieval time.
At the start, it is nearly impossible to predict
howdeeporbroadthescopeofaproductwill
become. If the IP being developed becomes a
commercial success, there will be high demand
for new variants for use in different environments
or applications. As the scope increases in
scale, the SCM system will need to cope. Two
techniques SCM systems use to address this are
lazy copying and reverse delta archiving.
Lazy copying recognises that when a variant is
first created it is identical to the original. A
pointer to the original is all that is created,
rather than a physical copy. As the variant is
modified new storage is reserved, and then only
15
TOOLS &SOFTWARE
to record the differences between it and the
original. This applies to a variant consisting of
any number of files so ensuring minimal storage
space requirements. Reverse delta archiving
is where the historical record of a file just consists
of the latest version of a file stored in its entirety
along with the difference - or delta - between
it and the previous version, and the version
before that and so on. Older versions are
recreated by taking the latest and applying the
relevant deltas in reverse order until the required
version is recreated. This technique
recognises that the most commonly accessed
versions are usually the most recent and also
that the differences between versions are often
fairly small. Like lazy copying, the reverse delta
technique aids performance by reducing both
disk space needs and computation time as the
size of the project increases.
So, by avoiding the creation of a physical copy,
variants constituting any number of files can be
created quickly - a key advantage in fast prototyping,
where system architects and product developers
can be working on separate ideas
alongside the main development stream. These
November 2009

TOOLS &SOFTWARE
prototype developments have to be isolated
from all other development streams until all or
parts of them are ready to be introduced back
into the main design. This can be a problem for
some SCM systems, but is a vital requirement to
allow engineers to innovate and prototype in
the way they want to. Again, lazy copying
helps by making it straightforward for just the
differences to be copied back into the main
development stream from the variant.
With the relative ease that differences can be
moved backwards and forwards between variant
streams, feature enhancements, bug tracking
and resolution is simplified too. New features
added, or bugs resolved during development,
can be applied easily and propagated
around the various development areas, and a
complete audit trail is preserved within the
SCM system.
Increasing product complexity has seen architects
and developers becoming more focused on
innovation in their specialist areas. To deliver
products, it is commonplace that third-party IP
is used for some elements of both hardware,
such as processor and interface IP, and software,
with drivers and middleware. So, for rapid pro-
■ IAR: ZigBee tool for sensing and control
applications
IAR Systems and Ember have teamed together
to deliver a reliable and easy to use ZigBee development
and debugging platform for sensing
and control applications such as smart metering
and home automation. Ember recently
launched the EM35x InSight Development
Kit. The EM35x Insight Development Kit is
built around ARM Cortex-M3 processor technology
and comes with the latest version of IAR
Embedded Workbench for ARM, a completely
integrated development environment for embedded
applications.
News ID 489
■ pls: UDE supports VaST’s virtual processor
models and tools
pls Programmierbare Logik & Systeme and
VaST Systems have established a cooperation
with the goal to further simplify the simulation
of automotive software applications by interfacing
their products. Developers use VaST tools
totyping benefits to be felt, these third party elements
have to be integrated into the prototype
as easily as possible. With agile development
techniques and a continuous development
cycle, new versions of third party IP can be fed
in from the software team and third party partners
almost continuously. With the right SCM
system, all these inputs can be added to a safe
area where engineers can look at the latest component
versions and assess whether they can be
used in the prototype. They can also access the
latest hardware elements and test them out to
see whether they are appropriate to be included
in the prototype.
Large organisations often struggle to maintain
the pace of innovation that they had when they
were smaller. Developing prototypes in either
hardware or software usually requires bringing
together far-flung design teams and system architects,
and dealing with the inherent communication
challenges. Making this a fast and
efficient process can be a struggle. SCM systems
are also being used to speed up the prototyping
process dramatically by linking sites and teams
around the world, rather than having to have a
prototype handled by one team in one place.
NVIDIA, for instance, uses SCM to link inter-
Product News
to create and simulate virtual prototypes for application
software development and to perform
precise architecture performance analysis. Their
ability to run real software applications at
near real-time speeds before hardware availability
reduces time-to-market.
News ID 443
■ The MathWorks: Simulink Control Design
with improved PID tuning features
The MathWorks announces the availability of
Simulink Control Design 3.0, equipped with
new features that automate the process of tuning
proportional-integral-derivative controllers.
These features are being released along with
new PID Controller blocks in Simulink.
News ID 493
■ Wind River adds CGL 4.0 compliance
for MIPS architectures
Wind River announces that Wind River Linux
3.0 for MIPS architectures complies with the
Carrier Grade Linux (CGL) 4.0 specification
November 2009 16
nal teams across multiple disciplines and multiple
global sites along with third party developers,
pulling in the right elements for the project,
regardless of the location.
The practical adoption of any SCM system has
to be achieved with the minimum impact on
the development process and on company resources
to stand any chance that it will actually
be used and that the designs and prototypes
are turned into the right products at the right
time for the market. And using the SCM system
well can significantly improve the efficiency and
innovation in developing prototypes, without
compromising the existing product lines. SCM
systems can remove a huge logistical burden in
managing the output of internal and external
teams from around the world. Design teams get
the resources they need quickly and give them
more room to innovate and push the boundaries
of what is possible in embedded designs.
Everything that is ever created is recorded -
whether it survives in the final product, or ends
up a failed experiment. Innovations in one variant
can be folded back into the mainstream
product lines, and bug fixes quickly propagated
to everywhere they should be. ■
from the Linux Foundation, a critical requirement
for the telecommunications and high-end
data networking markets. This includes MIPSbased
multicore processors from Cavium Networks
and RMI Corporation, and also extends
existing CGL 4.0 support for PowerPC and x86
architecture-based processors from Freescale
and Intel.
News ID 494
■ QNX pursues SIL 3 certification for
safety-critical systems
QNX Software Systems is pursuing IEC 61508
Safety Integrity Level 3 certification for the
QNX Neutrino RTOS. SIL 3 is considered the
highest level of risk reduction achievable on a
single programmable electronic system. IEC
61508 is well established in the industrial
process control and automation space, and is
becoming increasingly important in automotive,
heavy machinery, mining, nuclear, and
other applications.
News ID 495

■ LynuxWorks: new version of separation
kernel and hypervisor
LynuxWorks announces the release of Lynx-
Secure 3.1, the newest version of its separation
kernel and embedded hypervisor. This update
to LynxSecure takes advantage of new technologies,
including guest operating support for
the latest Microsoft Windows and the latest
Intel Core2 Duo systems.
News ID 498
■ Microsoft kicks off embeddedSPARK
2010 Challenge
Microsoft has launched the embeddedSPARK
2010 Challenge, a new competition designed to
foster creativity and innovation among the embedded
hobbyist and academic communities
globally. Based on the successful Sparks will Fly
competition, the embeddedSPARK 2010 Challenge
encourages contestants to demonstrate
innovative thinking within the theme of ‘Fun
and Games.’
News ID 510
■ dSPACE: real-time system for fast function
prototyping
All dSPACE MicroAutoBoxes now provide
more performance for prototyping ECU functions,
especially with large real-time models.
The performance boost comes from the IBM
PPC 750GL processor, which reaches faster
cycle times for model calculation with its
doubledLevel2cacheof1MB.
News ID 532
■ Hitex: evaluation with benchmarking
of performance and power consumption
The LPC1313-Stick from Hitex is the brand
new tool for evaluation of the ARM Cortex-
M3 based LPC1300 controller family from
NXP featuring a high level of integration and
low power consumption. The LPC1313-stick
comes with an un-limited HiTOP debugger,
GNU Arm compiler and the professional Tasking
compiler as well as a large selection of application
code. In addition, benchmarking is
easy with the included tools from EEMBC.
News ID 483
■ IAR: development package for
ARM Cortex cores
IAR Systems announces the availability of IAR
Embedded Workbench for Cortex-M, an integrated
development environment designed
specifically for ARM Cortex-M0, Cortex-M1,
and Cortex-M3 based cores, which provides a
comprehensive set of tools in a single package.
Based on the latest full license edition of IAR
Embedded Workbench for ARM 5.40, this
limited license edition is competitively priced
and helps keep the costs of equipping development
engineers with industry respected toolsets
to a minimum.
News ID 430
17
TOOLS &SOFTWARE
■ NI simplifies advanced motion control
National Instruments announces the new Lab-
VIEW NI SoftMotion Module, which simplifies
the development of advanced single- and multiaxis
motion applications, and new NI C Series
modules, which expand the connectivity of the
NI CompactRIO programmable automation
controller platform to hundreds of servo and
stepperdrivesfromNIandthird-partyvendors.
News ID 596
■ Enea announces OSE multicore edition
Enea announces the immediate availability of
Enea OSE Multicore Edition, an innovative kernel
design that combines the advantages of both
traditional Asymmetric Multiprocessing and
Symmetric Multiprocessing while avoiding the
disadvantages inherent in both programming
models. OSE Multicore Edition kernel delivers
on the ease-of-use promise of SMP when it
comes to simplicity, flexibility, application
transparency and debugging.
News ID 461
■ Actron: simplifying graphic displays
development
Distributor Actron announced that Beijer
Electronics is launching a new concept based on
their knowledge in HMI together with Hitech
Electronics’ experience in LCM. "Programming-Free
Display" enables simply-designed
user interfaces for embedded systems. With no
specific experience required, development time
and costs are dramatically reduced.
News ID 462
■ SYSGO: PikeOS aims at Common
Criteria EAL 7
As part of the Verisoft XT project SYSGO has
initiated the formal verification of its Safe and
Secure Virtualization product PikeOS, taking
aim at the highest level of security corresponding
to today’s Common Criteria EAL 7. The
new innovative verification technique uses Microsoft’s
VCC tool and includes a verifying C
compiler used to annotate PikeOS and assembly
code with assertions that always hold and
that can be proved correct by VCC. The verification
extends to both C and assembly code.
News ID 477
■ Trusted Logic: NFC protocol stack
for Android
Trusted Logic launches TRUSTED NFC software
platform for Google Android operating
system enabling mobile applications to use
handset NFC connectivity. It provides simple interfaces
for developing applications, either in native
or using Java. Trusted NFC can be ported on
any mobile operating system and speeds up the
integration process by offering reference implementations
on the main operating systems,
such as the one on Android that is now available.
News ID 600
November 2009
You CAN get it...
Hardware & software for
CAN bus applications…
PCAN-USB Pro
High-speed USB 2.0 interface with
galvanic isolation for connecting
up to 2 CAN and 2 LIN busses.
PCAN-miniPCI
CAN interface for Mini PCI slots.
Optionally with galvanic isolation.
Available as Single channel or Dual
channel version.
PCAN-Explorer 5
CAN/LIN interface
Universal CAN monitor,
symbolic representation, VBS
interface, integrated data logger,
functionality upgrades with addins
(e.g. Plotter & J1939 Add-in).
www.peak-system.com
Otto-Roehm-Str. 69
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Phone: +49 6151 8173-20
Fax: +49 6151 8173-29
info@peak-system.com

TOOLS &SOFTWARE
Different design patterns for
integrating Simulink with Stateflow
By Michael Carone, The Mathworks
■ Engineers who use Simulink and Stateflow
within model-based design often need to integrate
state machines and control logic designed
in Stateflow with Simulink blocks, subsystems,
and components. Common tasks include
calling a look-up table block from
Simulink to perform interpolation on a specific
Stateflow variable. Stateflow is often used to
enable or disable Simulink subsystems that represent
specific tasks, such as start-up and shutdown,
or individual controller types. Another
common procedure involving both Simulink
and Stateflow is controlling the behaviour of
system components, such as the guidance and
navigation system of an airplane or a set of sensors
located in an automobile. To complete
tasks and procedures like these requires a
seamless interface between Simulink and Stateflow.
Starting with R2008b, Stateflow users can
create and embed Simulink functions directly
inside their Stateflow charts. This article reviews
three design patterns for using Simulink functions
inside Stateflow: modeling algorithms,
scheduling tasks and controllers, and controlling
components.
Adding Simulink functions to Stateflow is a
straightforward process: you simply drag the
function into the Stateflow workspace and
then double-click the function to open a new
Simulink editor window. In the example shown
November 2009
This article describes three
design patterns for
integrating state machines
and control logic designed in
Stateflow with Simulink
blocks, subsystems, and
components: modeling
algorithms, scheduling tasks
and controllers, and
controlling components.
Figure 1. Left: Stateflow chart incorporating Simulink functions created using the Simulink
function button (the white icon in the left navigation bar). Right: Function details
in figure 1, two Simulink functions, init and
steady, are embedded inside the Stateflow
chart. The same syntax used to call graphical
functions, truth-table functions, and embedded
MATLAB functions is used to call Simulink
functions. Simulink windows opened in Stateflow
include the same functionality as standard
Simulink windows. The three design patterns
described below are arranged in order of complexity,
from simple algorithm development to
component-based design. Modeling Algo-
Figure 2. Design pattern for calling Simulink algorithms from Stateflow
18
rithms. Using a Simulink block or algorithm
modeled within a Stateflow chart is an efficient
way to include reliable Simulink algorithms
within your control logic. In figure 2, a
Simulink look-up table block is incorporated
into a Stateflow chart using Simulink functions.
The block is used to perform a linear interpolation
of one of the input variables to the Stateflow
chart. The state machine compares the
output of this function to another Stateflow

Figure 3. Design pattern for scheduling tasks modelled in Simulink
from Stateflow
Figure 4. Design pattern for controlling components within Stateflow
■ CMX: embedded software for
ColdFire processors
CMX Systems offers two RTOSes, two TCP/IP
stacks, five Flash File Systems and multiple USB
stacks for Freescale’s ColdFire processor family.
CMX-RTX is a truly preemptive, multi-tasking
RTOS offering one of the smallest footprints,
fastest context switching, and lowest
interrupt latency times available on the market
today.
News ID 604
■ Vector enters into partnership with
aquintos
Vector enters into partnership with aquintos.
The software engineering company aquintos,
located in Karlsruhe, puts its primary focus on
Product News
the development of the PREEvision product. Its
software tools are used in the design, development,
evaluation and optimization of E/E
architectures. From product definition to topology,
it considers the levels of functional
modeling and distribution, networking, power
supply, electrical system and wire harness.
News ID 592
■ NXP: online tools for rapid prototyping
ARM and NXP announce mbed.org and the
mbed microcontroller rapid prototyping tools.
Mbed is an online platform for fast, low-risk
prototyping of microcontroller-based systems.
The mbed tools launch with integral hardware
and software support for the NXP LPC1768
ARMCortex-M3 processor-based MCU, mak-
19
variable to determine whether the state machine should be in the S1 or
S2 state. There are several other possibilities for including Simulink algorithms
within Stateflow. For example, custom library blocks can be
added to Simulink functions. You can then add your own reusable
Simulink algorithms to the logic and call these algorithms throughout the
state chart. The blocks that can be added to Simulink functions are not
limited to those in the Simulink library; for instance, you can also add the
fast Fourier transform block from signal processing blockset.
Scheduling Tasks and Controllers. Stateflow is commonly used to
model schedulers that determine when certain actions take place. For example,
Stateflow can be used to schedule exactly when a system should
start-up, perform a certain operation, and then shut down. The tasks that
are performed when the system is in each of those states are often modelled
in Simulink. With Simulink functions, you can directly associate
these tasks with the corresponding state (figure 3). In this design pattern,
three phases of a process are represented by three Stateflow states. When
the system is in phase 1, the Stateflow chart executes the task that is modelled
in the Simulink subsystem (task 1).
After 60 seconds, the system enters phase 2, and task 2 is executed. After
another 60 seconds, task 3 is executed. A key advantage of this approach
is the readability of the Stateflow chart - for example, it is immediately
apparent that the task to be executed when in phase 1 is the task that is
modelled within the task1 Simulink function. Another application of this
design pattern is to activate different types of controllers based on the
state of the system. For example, in one state, the controller can behave
in an open-loop fashion. When the difference between the desired
response and the actual response reaches a certain threshold value, the
state machine can transition to the closed-loop state, at which point the
closed-loop controller, modelled in Simulink, is activated.
Controlling Components. Another common application for Stateflow is
to control the behaviour of components modelled in Simulink. Figure 4
shows two independent components represented by two parallel states in
Stateflow. These components can be either off or on. When one of these
components is switched on, the Simulink component is activated from
the Stateflow chart. The Simulink functions shown in figure 4 look very
similar to those shown in figure 3, with one major difference: the blocks
shown in figure 4 are model blocks, not subsystem blocks. Model blocks
link to models that can be developed and tested independently. These
blocks are important for componentized design and large-scale
modelling. ■
ing cutting-edge microcontroller technology
accessible to a wide audience.
News ID 475
■ TI: USB Stick based DSP development tool
Texas Instruments announces the availability of
the TMS320VC5505 eZdsp USB stick development
tool, which drops the cost of a full-featured
emulator and integrated development
platform. This enables rapid creation of DSP
applications including portable audio players,
voice recorders, IP phones, portable medical
devices, biometric USB keys, software defined
radios, hands-free headsets and metering
applications.
News ID 453
TOOLS &SOFTWARE
November 2009

MICROS & DSPS
Single-chip coherent multiprocessing
boosts embedded performance
By Mark Throndson, MIPS
November 2009
This article explains how the
MIPS32 1004K coherent processing
system brings together
MIPS multi-threading and
coherent SMP in a single IP
block to provide scalable,
high-density embedded computing
power.
■ Driving the performance of an individual
processor to the limits of the possible in a given
implementation technology is never easy or efficient.
The tried and true methods of faster
clocks, deeper pipelines, and bigger caches all
have silicon area and power dissipation costs
that get well into diminishing returns to get that
last 10% of performance. There are times
when there is no alternative but to turn up the
clock and upgrade the power and cooling subsystems;
but when a workload can be split
across multiple processors, the limits to maximum
total performance are pushed back, and
the design of the processing elements themselves
can be made simpler and more efficient.
While you see this approach today in PCs,
servers and workstations, this is just as true in
embedded SoC designs. In fact, many embedded
SoC designs today make use of multiple
processors, but do so in an application-specific
or loosely coupled manner. Until recently,
SoC design options for software-friendly multiprocessing
were severely limited. However,
with the advent of SoC design components
such as the MIPS32 1004K coherent processing
system (CPS), on-chip symmetric multiprocessing
(SMP) under a single operating system
has become a real design option, and system architects
need to understand its promises and
limitations. Exploiting parallel processors requires
parallel software, and parallel program-
ming is a model that creates some apprehension
with software engineers because not all existing
code was written for a parallel processing platform.
But there are several paradigms for parallel
software, some of which are already very
familiar to software designers, even if they do
not necessarily think of them as such.
Data-parallel algorithms are ways of attacking
a single basic computational problem by
carving up the data set to make use of more
than one processor, ideally up to a large number
of CPUs. The textbook case of a large data
set is a large input file or data array, but in
embedded systems, it can mean high I/O and
event service bandwidth. In some SoC
architectures, multiple sources of input data,
such as network interface ports, each of which
needs to be handled the same way, can be
statically assigned to multiple processors
running the same driver/router code to make
for natural data-parallelism.
When the power of multiple processors must be
brought to bear on a single data array or single
input stream, data-parallel algorithms that divide
and conquer the data are often used, such
as the simple example shown in figure 1. Such
algorithms are generally sub-optimal on a single
processor, but make up for their inefficiency
with scalability to exploit more computational
bandwidth. They make up for it in vol-
20
Figure 1. Data-parallel
programming model
ume. These algorithms have been shown to be
the most scalable approach to parallel computing,
but converting a working sequential
program to a data-parallel algorithm may be
trivial, difficult, or impossible, depending on
factors such as the dependency characteristics
of the program.
A system designer looking for higher performance
for an existing application would
most likely look to explicitly implement dataparallel
algorithms if the vast bulk of computational
work in the application is done in a relatively
small number of long runs of regular
computational loops. The emergence of multicore
x86 chips for PC, workstation and server
processors has generated research and investment
in a new wave of libraries and toolkits to
enable, and more easily exploit, parallel algorithms
on modest numbers of processors.
Many of these are open-sourced and portable to
embedded architectures such as MIPS. Open-
MP extensions to gcc for data-parallel C/C++
as well as FORTRAN are becoming a part of the
standard GNU compiler collection.
Another paradigm, which will be referred to
here as control-parallel programming, is to split
the work of a program by task, rather than by
input. If an automobile factory where 100
workers are each given a car to build can be seen
as a metaphor for a 100-way data parallel

Figure 2. Control-parallel programming model
Figure 3. Concurrent multitasking
MICROS & DSPS
Figure 4. SMP task distribution across multiprocessor resources
algorithm, the analogous metaphor for a control-parallel program
would be a factory with a single assembly line consisting of 100 stations,
each staffed by a worker performing a different task that is 1/100 of the
assembly work. A simple example of a two station implementation is
shown in figure 2. The assembly line approach is generally more
efficient, but there is a limit to how far one can divide up the work of
assembling a single car. This limitation is significant for scientific codes
that one would like to scale to thousands of processors, but not generally
an issue with modestly parallel SoC architectures for consumer
applications.
Even without taking parallel processing into consideration, software
engineers will often break programs up into phases. It makes for easier
coding, debugging, and maintenance by teams of programmers, and it
reduces pressure on instruction memory and caches. In many cases, the
control-parallel decomposition of a problem has already been taken to
the level of OS-visible tasks. The single command cc on a UNIX-like
system invokes, sequentially, a C language pre-processor, a compiler, an
assembler and a linker. On an SMP multiprocessor, several of these can
be run simultaneously, with each successive program using the output
of the previous phase as its input, using files or, better still, the software
pipes that have long been a feature of UNIX-like operating systems,
including Linux. When decomposition into independently run tasks has
not already been done, some software engineering must be done to
make the phases of an application visible to the operating system and
21
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MICROS & DSPS
the underlying hardware, and to explicitly pass
data from one task to another when its ownership
passes from one phase to another. But
there should be no need to rethink or rework
the algorithms of the constituent phases, as is
generally required for a data-parallel decomposition.
Coarse-grain task decomposition can
be done in terms of processes communicating
via files, sockets, or pipes. For finer-grained
control, the POSIX thread API, pthreads, is
widely used, and is supported by a broad
range of operating systems, including Linux,
Microsoft Windows, and many real-time operating
systems.
Complex, modular, multitasking embedded
software systems will often exhibit serendipitous
concurrency, such as that illustrated in figure
3, even if it was not a design objective. The
overall mission of the system may involve the
operation of multiple tasks, each of which has
a distinct responsibility, responding to a distinct
set of inputs. Without a time-sharing operating
system, these tasks would each have to run on
a separate processor. On a time-sharing
uniprocessor, they run in alternating timeslices.
On a multiprocessor with an SMP operating
system, they can run concurrently across
as many processors as are available.
Another form of parallel processing that has become
so commonplace that it is sometimes not
even thought of as parallel is distributed computing,
of which network client/server models
are by far the most common paradigm. Clientserver
programming is basically a form of
control-flow decomposition. Rather than performing
all of a computation itself, a program
task connects and sends work requests to one or
more specialized tasks in a system which are
designated to perform specific jobs. While
client/server programming is most commonly
done across LANs and WANs, communications
between tasks within an SMP SoC follow the
same paradigm. One can use unmodified
client/server binaries communicating by
TCP/IP via on-chip or null loopback network
interfaces, or more efficiently by using local
communications protocols that pass data
buffers in memory. In practice, any of these
techniques may be used alone, or in combination,
to leverage the power of an SMP-based
platform for a given application. One could
even construct a data-parallel array of distributed
SMP servers, each of which implements a
control-flow pipeline. But for such a scheme to
be efficient there would need to be a very large
workload and data set.
In SoC systems where parallelism by static
physical decomposition of tasks onto processors
is possible (e.g. one processor core per input
port), the assignment of parallel tasks to processors
can be done in hardware. This reduces software
overhead and footprint, but provides no
flexibility. Similarly, if an embedded application
can be statically decomposed into clients and
servers communicating across an on-chip interconnect,
the only system software required to
tie the system together would be message-passing
code that implements a common protocol
between processors. The message passing protocol
provides some level of abstraction that can
enable configurations with more or fewer
processors to run a common base of application
code, but for any given configuration, the load
balancing between processors is as static as the
hardware partitioning. For more flexible parallel
system programming, software distribution
of tasks across a multiprocessor system with
shared resources is needed.
As the name implies, SMP operating systems
have a symmetric view of the system. All
processors see the same memory, the same I/O
devices and the same global operating system
state. This makes migration of programs from
one processor to another extremely simple and
November 2009 22
efficient, as shown in the simple example in figure
4, and makes load balancing easy. With no
additional programming or system administration,
a set of programs that multi-tasks on a
single CPU using time-slicing will run concurrently
on the available CPUs of an SMP system.
An SMP scheduler, such as that of Linux, will
switch programs on and off of processors so
that all make progress in a fair manner.
A Linux application that runs as multiple
processes needs no modification to take advantage
of SMP parallelism. In most cases, no
recompilation is required; the exception being
binaries that were statically linked with nonthread-safe
libraries. An SMP Linux environment
provides a number of tools that allow a
system designer to tune the way tasks share the
available processors. Tasks can have their priorities
raised and lowered, and can be restricted
to run on arbitrary subsets of processors.
With appropriate kernel support, they can request
the use of different real-time scheduling
regimes.
UNIX-like operating systems have always allowed
applications to have some control over
the relative scheduling priority of tasks, even in
uniprocessor time-sharing systems. The traditional
nice shell command and system call have
been augmented in Linux with more elaborate
mechanisms to manipulate the priority of
tasks, groups of tasks, or specific users of a system,
should it be necessary to second-guess the
OS. Additionally, in multiprocessor configurations,
every Linux task has a parameter that
specifies what set of processors may schedule
the task. By default, that parameter is the full set
of processors in the system, but, like priority,
this CPU affinity can be controlled either by the
taskset shell command, or by explicit system
calls to manipulate the “CPU affinity” of tasks.
An SMP system paradigm requires that all
processors see all of memory at the same ad-

dresses. For simple, low-performance processors,
this is not too difficult to accomplish. One
simply puts the instruction fetch and load/store
traffic of all processors on a common memory
and I/O bus. This simplistic model breaks
down pretty quickly with increasing numbers
of processors however, as the bus quickly becomes
a performance bottleneck. And even in
uniprocessor systems, the bandwidth requirements
for instructions and data of high-performance
embedded cores dictate that cache
memories be used between main memory and
the processor.
A system with independent per-processor
caches is no longer naturally SMP. When one
processor cache contains the only copy of the
most recent value of a location in memory,
there is a basic - and dangerous - asymmetry.
Cache coherence protocols must be added to
the system to restore that symmetry. In very
simple systems, where all processors are connected
to a common bus, it is sufficient for all
cache controllers to monitor the bus to see
which cache owns the latest version of a given
memory location. In more advanced systems,
such as the MIPS32 1004K CPS, processors are
connected to memory using point-to-point
connections to a switching fabric rather than a
bus. Cache coherence thus requires more sophisticated
support. The 1004K coherence
manager imposes a global order on memory
transactions and generates the necessary intervention
signals to maintain cache coherence
among multiple 1004K processor cores. The
1004K processors thus see a symmetric view of
memory. An SMP operating system such as
Linux can freely migrate tasks and dynamically
balance processor loads.
In an embedded SoC, a substantial portion of
overall computation can be spent in interrupt
service. This implies that good load balancing
and performance tuning requires control, not
only of where program tasks are allowed to run,
butalsowhereinterruptserviceistobeperformed.
The Linux operating system has an
IRQ affinity control interface that allows users
and programs to specify which processors are to
be used to service a given interrupt. To be usable,
this interface requires that the underlying
system hardware provide a means to selectively
route interrupts to processors. The 1004K
global interrupt controller provides this capability
for the 1004K CPS.
Cache coherence infrastructure is useful, not
only between processors for symmetric multiprocessing,
but between processors and I/O
DMA channels. While RISC architectures such
as MIPS32 have features to support softwarebased
I/O coherence, this requires that DMA
buffers be processed by the CPU before or after
each I/O DMA operation. This processing has
23
MICROS & DSPS
a measurable performance impact on I/O-intensive
applications. In the 1004K CPS, connecting
I/O DMA to memory via an I/O coherence
unit allows DMA traffic to be ordered
and integrated with the coherent load/store
flow, eliminating the software overhead.
In SoC design, as elsewhere in life, there is no
suchthingasafreelunch.The1004Kcoherence
manager imposes order and sanity on memory
traffic between processors, I/O, and memory,
but in doing so, it adds cycles to the memory
access time experienced by the processor.
Ordinarily, this would always result in additional
lost processor cycles when the pipeline
stalls, waiting for the cache to be filled with instructions
or necessary data. But the 1004K
platform implements the MIPS multi-threading
architecture first pioneered in the MIPS32
34K core family, which allows a single core to
execute multiple concurrent instruction
streams.
Each individual core within the 1004K CPS includes
support for two hardware threads via
VPEs, virtual processing elements that look just
like a CPU to operating system software. The
two virtual processors share the same cache and
functional units, and interleave their execution
on the pipeline. If one VPE is stalled waiting for
a cache fill from memory, the other can execute
to keep the pipeline busy. In effect, the multithreading
capability of the 1004K processor allows
it to take back cycles otherwise lost to the
latency of the coherent memory subsystem.
Since the 1004K processor VPEs look like fullblown
processors to software, up to and including
having independent interrupt inputs,
the same SMP operating system logic that manages
multiple cores can be exploited to manage
their constituent VPEs. At the highest level of
system administration, a dual-core 1004K system
with all VPEs active looks to be a 4-way
SMP system. Software that has been written or
configured to exploit SMP can naturally exploit
multi-threading, and vice versa.
While the view of system resources remains
symmetric, it is true that two threads competing
for the use of a single processor pipeline will
achieve lower performance than two threads
running on independent cores. This situation
has existed for years in server systems, where coherent
clusters of multi-threaded CPUs are not
unusual, and the SMP Linux kernel for the
1004K is equipped to do the necessary load-balancing
optimizations. If optimizing for power
consumption, the scheduler can load work onto
the virtual processors of one core at a time, so
that the others can remain in a low-power state.
If optimizing for performance, it can spread
work across distinct cores first, only loading up
multiple VPEs per core once all cores have an
active task to run. ■
November 2009
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MICROS & DSPS
Accelerating early stages of the design
cycle with i.MX processors
By Tony Eriksson, Future Electronics
■ For good reason, the i.MX family of microprocessors
from Freescale Semiconductor is a
popular choice for embedded systems that require
high performance and low power consumption
at a reasonable cost. These devices are
highly sophisticated processors with strong
compute and data-throughput capabilities. But
the very power and sophistication of the i.MX
makes it all the more important to approach the
design process correctly. With so many options
and configurations available to the designer,
there is a risk of failing to take advantage of features
or capabilities that could be useful to the
application. So before beginning a new design
project, it will pay every design team to ensure
that they have the right combination of hardware,
knowledge and resources available to
them from the start.
First, it will help to understand what kind of
processor we are dealing with. The i.MX is an
ARM-based application processor that aims for
high integration and low power consumption
combined with powerful performance. It is derived
from the Dragonball MX series processors,
and can be traced back to devices introduced
in 1996 by Freescale’s predecessor company
Motorola. Then, the parts were aimed at
the handheld market, where the requirement
was for low power consumption combined with
high performance. Today the i.MX family can
be used in a wide variety of applications. To
meet this variety of needs, it is divided into
three groups: i.MX2x, i.MX3x and i.MX5x.
November 2009
The i.MX family
of microprocessors from
Freescale is a popular choice
for embedded systems that
require high performance
and low power consumption.
This article describes
some of the most useful
resources and tools for
i.MX design teams.
Within these families there are further sub-divisions
targeting automotive, industrial and
consumer applications. With so many different
variants of the core product, it is possible to
find a part with features that closely match the
requirements of almost any embedded application
(figure 1). Having chosen the i.MX device
that is best suited to the requirements of
the application, the product design process is
readytostart.Itisalwaystemptingtostartadesign
project by developing a proof-of-concept
of the end product. Strangely, design projects
proceed quicker if the first action of the designer
is to work with a board that is not a prototype
of the end product: a product development
kit (PDK) or evaluation kit (EVK) provided
by Freescale. (For the purposes of illustration,
this article will describe in detail only a
PDK, the more feature-rich and powerful of the
two types of kit. It should also be noted that
i.MX development kits are available from
third-party companies other than Freescale.)
The Freescale PDK comes with start-up software
and tooling pre-loaded and configured for
use out of the box. Even though you are unlikely
to use all the software and schematics,
they give you a feel for the i.MX. In addition,
the PDK board gives you a benchmark for comparing
the performance of your prototype.
Freescale makes several operating-system board
support packages (BSPs) available for download
with every i.MX PDK. You can also order the kit
pre-loaded with Windows CE or Linux. The
24
Figure 1. Freescale roadmap
for the i.MX family
BSP is an important part of the PDK, since it
enables to start application development early
in the design process. It includes a tool chain,
operating system (OS) kernel, middleware,
applications and board-specific modules. Again,
BSPs for various i.MX processors are available
from a variety of third-party OS vendors, such
as Wind River for its VxWorks OS, QNX for its
Neutrino OS and MontaVista software for
Linux. For the newly released i.MX25 PDK, Future
Electronics exclusively offers Freescale
eCos OS. eCos is a fast, reliable real-time operating
system that is both extremely configurable
and has a very small memory footprint.
For users who are migrating to an i.MX processor
from a less powerful microcontroller, the
decision about platform software is new and
critical. Typically, legacy microcontroller projects
either use a proprietary scheduler, a small
operating system or no platform software at all.
When migrating to a high-end processor, it is
tempting to port the previous scheduler or operating
system to the i.MX. But there are huge
advantages to the powerful operating systems
that such a processor can support. Linux, in
particular, is a very attractive option, as it gives
you access to a huge quantity of free (opensource)
code. By continuing to use a proprietary
or small OS, you are more or less restricted to
the content of your own libraries. Some established
OS vendors warn developers that there is
a high risk of wasting both time and money in
using an unsupported open-source OS such as

Figure 2. Development environment using the i.MX25 PDK
Linux. They will claim that developers can accelerate
the design cycle and reduce risk by
using a commercial, out-of-the-box real-time
OS that is fully supported by the vendor.
Nowadays, however, the quality of the embedded
Linux distributions from semiconductor
manufacturers such as Freescale is extremely
good. You can also get almost the same level of
support on Linux as you would expect from any
commercial OS by buying a distribution from
a Linux vendor such as MontaVista.
So, what can you expect from the PDK once
you have laid your hands on it? The development
kit consists of three boards: a CPU
board, a debug board and a so-named personality
board. The CPU board contains the i.MX
applications processor, memories and power
management circuitry – a range of CPU boards
are available that carry processors such as the
i.MX25, i.MX27, i.MX31 and i.MX35. The
CPU board can run on its own without the
debug and personality boards. The debug
board enables easy and quick debugging of
both software and hardware. One debug board
is compatible for use with a series of different
CPU boards. The function of the personality
board is to model real products. This means
that it contains various interfaces and functions
that suit the i.MX variant on the CPU board.
For example, the personality board for the
i.MX25 processor, which is aimed at industrial
and consumer applications, contains wireless
(Bluetooth, 802.11) and wired (USB, CAN, Ethernet)
connectivity interfaces, a TFT display, a
camera module, external memory card interfaces,
connectors for headphones, TV-out and
docking, and a microphone.
Freescale usefully makes the schematics for each
of the boards available free for download from
the internet. Its board designs are deliberately
made to resemble customer end products, and
so the ability to copy and then refine the
Freescale schematics can usefully accelerate the
board design process. If you use components in
the end product that are also on one of the PDK
boards, you will know that the software supporting
these components in your end product
will work. This section outlines the development
tools required for an i.MX project, but
there are a number of sources of information
for more detail on the set-up process for new
projects. The most important documentation
about setting up the host is the Linux Target
Image Builder (LTIB) manual; this is included
in the kit and can be downloaded from the
Freescale website. First, then, the basic resources
you will need (figure 2). In hardware
you will need PC, Ethernet cable, serial cable,
i.MX PDK, and JTAG debugger. The software
must contain the latest Linux BSP, which
should be downloaded, since the one preloaded
on the kit could be an older version,
VMWare player, available free from VMWare,
and a PC Linux distribution supported by the
kits LTIB. For the sake of illustration, figure 2
shows Ubuntu Linux v8.10. ATK (advanced
tool kit), a program used to flash images to
Freescale development boards via a serial or
USB port, and a serial terminal program, to
communicate with the boot-loader, should
also be included.
First, you will need to install the required programmes
on the PC. Linux distributions that
support LTIB are downloadable from the internet
as VMWare images that are configured to run
in the VMWare player. Next, install the LTIB on
the Linux OS. LTIB is used for creating and building
Linux target images. LTIB, a free software programme,
is available from, and maintained at,
www.bitshrine.org. Now you will set up the communications
interfaces to the system. At this stage,
you should decide whether to implement an NFS
server. (NFS stands for network file system and is
a client/server system that allows the i.MX PDK
to access files over a network and treat them as locally
stored.) Using an NFS development configuration
is the right choice for most develop-
25
ment projects, because it means not having to
store and edit files on the kit itself. In some realtime
applications, however, timing could be
skewed by the delay produced when data is transmitted
over Ethernet. The PDK is shipped with
a pre-installed boot-loader, kernel and file system
as shown in figure 2 – this helps save time at the
start of the development process.
In a real end product, the boot-loader will generally
load the kernel from NAND, NOR or
SD/MMC memory at start-up. For debugging
purposes, the boot-loader also enables the
kernel to be downloaded via the NFS server. For
the same reason, the Linux kernel provides access
to the file system via the NFS server when
you have the file system configured for on target
memory. After experimenting with the
board, it can be helpful to create a fresh, clean
environment on the board: to do this, the BSP
is able to revert to known good configuration
files for the entire BSP or for specific elements
such as the kernel or the boot-loader. These
image files are downloadable to the board
with the ATK or a JTAG debugger. With regard
to JTAG debuggers, it is good practice to connect
the device directly to the board, as this allows
for faster downloading and provides better
debug options. ■
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MICROS & DSPS
November 2009

FPGAS,PLDS & ASICS
The drive to lower power opens up
new FPGA applications
By Christian Plante, Actel
■ Field-programmable gate arrays (FPGAs)
are growing up. As process technology continues
to improve, device sizes shrink and designers
pack more onto silicon real estate, FPGAs
have found themselves, in recent years, the centre
of attention. Their differentiation in terms
of flexibility and time-to-market are finding
new applications - and responsibilities.
The shift towards portability and power-conscious
electronics has led to the demand for
low-power components of every variety, and
that now includes FPGAs. Today, power is a
more important design consideration than
performance. For some vendors this has meant
offering incrementally lower power devices,
with next-generation devices being 60 percent
lower power than previous generations. This
trend is taking root in a variety of applications.
In medical devices, where there is a clamour for
portable medical equipment for quick and
easy diagnosis. In displays, which are today
being incorporated into innumerable systems.
In industrial equipment, where motor control
design is seen as a key way to improve the overall
energy efficiency of products and ultimately
the world.
That FPGAs are being designed into such applications
is new. Designers traditionally relied
on application-specific integrated circuits
(ASICs), not FPGAs, to meet their low-power
November 2009
Power is often a more important
design consideration
today than performance.
Portable, power-conscious
electronics demands lowpower
components of every
kind, a demand increasingly
met by FPGAs. This article
highlights the trend and technology
by examples drawn
from many fields.
constraints. But hardwired ASICs, with their
longer time-to-market, rising non-recurring
engineering charges (NREs) and lack of flexibility
to address changing standards and latestage
design modifications, are riskier and
often impractical for applications with short
product life-cycles or evolving standards. Similarly,
the complex programmable logic devices
(CPLDs) used in some low-power applications
are losing their effectiveness, due to relatively
high costs and the increased demand for highend
features and extra logic. CPLDs do not
offer the level of integration, flexibility, or
sophistication required for most of today’s
applications. As a result, designers are looking
to FPGAs as competition intensifies and timeto-market
asserts a greater impact on product
success. In fact, designers are finding that a lowpower,
reprogrammable solution is required to
adapt to evolving standards, speed time-tomarket,
offer products with multiple personalities
and deliver the footprint and power -
consumption required for the next cutting-edge
electronics designs.
Certainly, not all programmable logic is well
suited to address low-power needs. In fact,
some of today’s “low-power” FPGAs draw upwards
of 30mA, which is often an order of magnitude
or two higher than typical power-sensitive,
battery-operated applications can tolerate.
SRAM-based devices experience well-docu-
26
mented inrush and boot-up configuration
power spikes during system initialization that
can drain a battery quickly. But single-chip,
flash-based devices do not require an external
configuration device (i.e. boot PROM or microcontroller)
to support device programming
at every power-up cycle. And the live-at-powerup
feature eliminates the need for an external
device to assist in system boot-up. Removing
the additional parts required by SRAM-based
FPGAs not only reduces board space and
system power consumption, but also increases
reliability, simplifies inventory management
and lowers total system costs by as much as 70
percent compared with similar SRAM-based
FPGA solutions.
Once the FPGA is on and configured, power
consumption takes two basic forms - static and
dynamic. Static power consumption is the
current drawn by an FPGA when it is powered
up, configured and doing nothing, while dynamic
power is consumed when devices are actively
working. Until recently dynamic power
was the dominant source of power consumption.
Once helping to manage the dynamic
power problem, device supply voltages (Vcc)
had scaled downwards with process shrinks and
subsequent lower system voltages, but the days
of continued scaling are coming to a close.
Compounding the issue, each process node
shrink means additional static power con-

Figure 1. Until recently dynamic power was the dominant source of power consumption.
sumption for transistor-heavy SRAM-based
FPGAs. This is due to worsening problems like
quantum tunnelling and sub-threshold leakage,
which create real challenges for devices targeted
to power-conscious applications. And, with
leakage worsening, static power has begun to
dominate the power consumption equation as
the biggest concern. So where the SRAM cell
structure incurs substantial leakage and requires
power-consuming configuration memory, by
contrast, flash-based cells have no leakage path
and thus have 1,000 times lower leakage per cell
than SRAM.
To address some of these power concerns, several
suppliers of SRAM-based FPGAs claim to
offer single-chip, flash-based solutions. These
hybrid solutions are merely combinations of
flash memory components with the underlying
SRAM FPGA technology - either integrated
with the FPGA die into a single package or, alternatively,
stacked or placed side-by-side. Unfortunately,
the FPGA array is still volatile and
is subject to the power drawbacks associated
with this type of device. With these solutions,
DISCRETE DEVICES
ANALOGUE ASSPs
SINGLECHIPINVERTER&MOSFETS
CONTROLLER & DRIVER
the embedded flash memory blocks control
only the initial configuration of the devices
during power-up. Certainly, both the siliconin-package
(SIP) and the multichip package
(MCP) hybrid approaches overcome some of
the limitations of traditional SRAM-based
solutions by providing a smaller footprint, a
minor reduction in power consumption, and
small advances in power-up time and security.
But these are only incremental improvements
over their pure SRAM-based peers.
True non-volatile FPGAs are those that contain
a non-volatile FPGA array, reducing power consumption,
improving response times, and delivering
unparalleled reliability and security. Because
true non-volatile flash-based FPGAs do
not use millions of power-hungry SRAM configuration
bit cells, they have significantly
lower static power than SRAM-based solutions,
making them ideal for power-sensitive applications.
In fact, the many flavours of flashbased,
low-cost FPGAs include devices that
have been optimized for power, speed, and I/O,
some of the fundamental design requirements
MICROCONTROLLER
FIELD-ORIENTATED CONTROL
for power- and cost-sensitive design. Portable
medical equipment made big news at the 2008
Beijing Olympics when companies, such as GE,
were test-driving portable MRIs and other
imaging and diagnostic tools at the Games.
FPGAs play a big part in this development,
allowing programming of various features and
design for differing geographical standards,
making them devices with multiple personalities,
while at the same time keeping power low
as well as the design costs. This trend towards
miniaturization and portability for home,
clinical, and imaging medical devices presents
a significant opportunity for medical equipment
designers to use FPGAs in developing
efficient and flexible designs.
Medical devices have high-reliability requirements,
demand multi-functionality (integrated
capabilities), require data logging and transmission
capabilities - and yet must consume the
lowest amount of power. In the most basic
form, portable medical devices are all batteryoperated,
micro-controlled handheld devices
that take and analyze measurements using
various biosensors that are used in a patient’s
treatment plan. Home-based and consumer
medical devices - digital blood pressure meters,
blood gas meters, and blood glucose meters -
have been traditionally used for testing and
monitoring. Today, medical devices are expected
to do much more than just test and
monitor. Some now log and analyze data and
communicate accurate results to the health
provider. Blood pressure meters benefit from a
more extensive data-logging feature as well as
communication ports for real-time information
sharing with the health provider. Insulin meters
are now equipped with communication ports
(IR/wireless) to transfer real-time measurement
to the PC or to the insulin pump to effectively
treat the disease. In figure 2 the functional
blocks represented with shading represent
some possible functions that can be implemented
in FPGA devices. These functions can
either be individually addressed as needed by
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27
FPGAS,PLDS & ASICS
November 2009

FPGAS,PLDS & ASICS
Figure 2. The functional blocks represented with shading represent some possible functions that
can be implemented in FPGA devices.
Figure 3. Careful design considerations in managing power using FPGAs as a complex LCD
controller, for example, can reduce power consumption.
smaller low-power reprogrammable FPGA devices,
or be integrated into larger FPGA devices.
These ultra-low-power FPGA families offer gate
capacity from 15k gates up to 3 million gates.
Pressure to reduce healthcare costs is butting into
the demand for more portable devices, which,
when deployed in the home, can save the system
money. But these devices need to be low power,
flexible and cost-effective for wide deployment.
Let us look at another application that is increasingly
leaning on programmable logic to
ensure flexibility and time-to-market speed:
displays. Lower costs and ease of mass manufacturing
have increased LCD panel demand in
medical markets. When creating these devices
to meet consumer demands, designers select
LCD panels based on critical factors, such as
size, resolution, reliability, power consumption,
and product lifecycle. As newer displays with
enhanced capabilities and features are continuously
launched, designers face challenges in
keeping up with technology by redesigning the
display controller. Redesigning is expensive
November 2009
and can significantly increase time-tomarket;
therefore, designers need solutions
that will enable them to incorporate the latest
technology with minimal cost and effort.
In portable devices, LCDs can consume up to
50 percent of the power budget of an application,
escalating the need for a power-efficient
solution. Power-aware attention to the design
does not rule out the use of FPGAs, which are
often seen as power-inefficient choices. Careful
design considerations in managing power using
FPGAs as a complex LCD controller, for example,
can reduce power. Some FPGAs offer
low-power advantages, down to 5mW while retaining
the contents of the system memory and
data registers. As a result, the FPGA approach
can enable both the LCD panel and the controller
to function in a power-saving mode with
the LCD data and backlight disabled, representing
significant battery savings for LCD applications.
The development of smaller and
more powerful motors, along with recent advances
in high-energy batteries, has opened new
28
marketstoarangeofmotorizedproducts,from
home appliances and electric vehicles to entertainment
devices and toys. New designs for AC
and DC motor control must be highly efficient
and consume little power in order to provide
longer operation without affecting performance
quality. The need to implement smaller, more
cost-effective motors in traditional motor applications
is also influencing electronic motor
control techniques for the industrial sectors. Expensive
computer and power electronics have
been significant obstacles to overcome for
motor control applications. Tremendous technology
improvement in semiconductor
processes and integration helps designers face
these challenges, specifically through integration
that combines analog, flash memory, and
FPGA fabric in a monolithic device. For the first
time, engineers can combine the motor control
analog front-end, high-speed flash look-up
tables and deterministic algorithm processing
capabilities of programmable logic into a
single-chip solution.
While the biggest growth segment of electronics
design today is low power, that design imperative
until recently came at a price, which
often included designing out performance,
functionality or missing out on integration opportunities.
Increasingly, however, those traditional
trade-offs are not so onerous. FPGA vendors
have integrated microcontroller and microprocessor
cores into their devices. Some of
these approaches feature very low operating
current and static power, consuming only
24μA in static mode and 3μA in sleep mode.
The Flash Freeze mode that Actel employs,
which enables easy entry and exit from ultralow-power
modes while retaining SRAM and
register data, reduces quiescent current to
20μA. The feature also allows instant on/off cycling
of the processor core for maximum performance
and minimum power consumption.
This is approximately 200 times less static
power than competitive FPGA offerings and
delivers more than 10 times the battery life of
the leading programmable logic devices in
portable applications.
There is a similar advantage where analog
meets digital. Mixed-signal FPGAs integrate
programmable logic, RAM, flash and analog
onto a single chip, while lowering overall system
power. A flash-based approach to mixed-signal
FPGAs does not require additional configuration
nonvolatile memory in order to load the
device configuration data at every system
power-up, which reduces cost and increases security
and system reliability. Increased functionality
can remove several additional components
from the board, such as flash memory,
discrete analog ICs, clock sources, EEPROM,
and real-time clocks, thereby reducing system
cost and board space requirements. ■

■ Power management is becoming very important
due to multiple factors. For mobile
handheld embedded systems, there is always
pressure to increase battery life and at the same
time offer more features. Battery chemistries are
not improving at the rate that is needed to fulfil
this requirement, so the pressure is on silicon
vendors to deliver better performance at lower
power. At the same time, to meet the time-tomarket
requirements posed by shrinking design
cycles, there is a need to offer flexible and
programmable devices at lower power.
Moreover, green movements are emphasising
the need to reduce battery waste, which translates
to embedded systems that require fewer
battery changes. There are also government regulations
(for example: Energy Star) across the
globe to reduce stand-by current in appliances.
The next generation of embedded systems is
going to need extremely low active and sleep
power consumption while simultaneously increasing
the amount of flexibility and programmability
needed to meet time-to-market
requirements.
Apart from lower current consumption, there
is also a need to lower system voltage. A few
years ago, the standard for minimum operating
voltage was 3.3V. Today, it is 1.8V. Charting this
trend, it is realistic to extend it into the sub-volt
range for future devices. This opens up the abil-
ity to build SoC-based designs with a single AA
or AAA battery (whose end-of-life voltage is
around 0.9V). Although some SoC-based designs
can run at 1.8V today, quite often the analog
performance degrades with such low voltages.
For handheld battery-powered designs
that require good analog performance, systems
that can run at below 1 volt voltage and still
meet the analog performance requirements,
offer the ability to move to a single AA or AAA
battery. This translates to lower cost to the
consumer and fewer batteries.
Sub-volt operation can be achieved when the
embedded SoC device has a built-in boost converter
able to boost the input voltage (example:
0.9V input voltage) to a higher system level
voltage (example: 3.3V). In this mode, it is important
that the noise from the boost converter
does not affect the performance of analog peripherals.
Figure 1 shows the system level connections
for an integrated boost converter that
is a part of a PSoC 3 programmable systemon-chip
from Cypress Semiconductor.
Having an integrated boost
converter that can accept
sub-volt input voltages has
the following advantages:
ability to run the system
from a single AA or AAA
battery, ability to provide a
29
FPGAS,PLDS & ASICS
Flexible power system management
capabilities for embedded systems
By Palani Subbiah, Cypress
This article shows
how programmable logic
devices are well suited to
enable flexible and efficient
power management
functions, especially for
battery-powered embedded
systems.
guaranteed minimum system voltage even
with a varying supply voltage, and ability to use
the boost output voltage to run other circuitry
in the system that needs higher voltage. Example:
LCD glass, sensor circuits, etc. Having a
wide supply voltage range that spans from 1.8V
(0.9V with boost enabled) to 5.5V provides
maximum flexibility to the user due to the following
reasons: it can span standard battery
voltage ranges for most common batteries
through their end-of-life voltage as shown in
table 1, it is compatible to legacy system voltages
of 3.3V and 5V, and the upper end of 5.5V provides
margin above 5V for rail-to-rail measurements
of signals from legacy systems.
The wide external supply voltage, while maintaining
a stable low core voltage for the silicon
can be accomplished by providing built-in
low dropout regulators within the device.
Moreover having separate internal regulators
for digital and analog domains ensures that
analog performance is not compromised due to
noise from the digital power rails. Figure 2
shows the system level connections and inter-
Battery type Start of life voltage End of life voltage
Single AA/AAA 1.5V 0.9V
Dual AA/AAA 3.0V 1.8V
CR2032 Coin Cell 3.0V 2.0V
Table 1. Standard battery voltage ranges for most common batteries
November 2009

FPGAS,PLDS & ASICS
Figure 1: System level connections for boosting an external low voltage
to a higher internal voltage
Figure 3. Independent power supply voltages for each I/O bank provides seamless interfacing to
devices that might operate at different voltages.
nal regulators that accommodate a wide supply
voltage range. In figure 2, Vddd and Vdda can
vary from 1.71V to 5.5V while the built-in
analog and digital regulator ensures that the
core still runs at a stable low voltage. When
properly designed, this system also ensures the
same analog performance across the entire
supply voltage range.
To allow interfacing to other devices in the system
that might have different system voltages,
an SoC needs to have separate I/O power rails
that can be independently set to any voltage
within a wide voltage range. An SoC that has 4
I/O banks, with each I/O bank able to be driven
with any voltage from 1.8V to 5V, provides
seamless interfacing to other devices on the
PCB as shown in figure 3. While there continues
to be a myth that programmable systems
are power hungry, well-thought-out programmable
SoCs can have world class power numbers
that match stand-alone MCUs. Keeping the
end customer application in mind, the power
modes that are desirable. Active mode as shown
in table 1 is the normal operation mode of the
system when it is used actively by the user. A
programmable SoC will allow the capability to
selectively disable unwanted peripherals in this
mode. In alternate active mode, a selected
fewer number of peripherals are active. This
providesareducedpoweractivemodethatcan
be entered from the regular active mode. Upon
exit from this mode, the system returns to regular
active mode. An example use case for this
is a situation where an embedded system with
a display continues to operate while the display
alone is turned off. When the display needs to
be turned off, the system will enter alternate active,
where the peripherals needed for the display
are turned off.
Sleepisacommonlyusedmodeinbatterypowered
embedded systems. This is an extremely
low power mode, where all peripherals
November 2009 30
Figure 2. System level connections for internal regulators
are in low power state, while a real-time clock
can be maintained. This mode is also used for
systems that need to be duty cycled between
active and sleep constantly. An example use case
is a temperature sensor that needs to update its
reading every minute. The system wakes up
every minute, takes the reading and goes back
to sleep. This results in reduced average power.
Hibernate is the lowest power consumption
mode of the device while memory contents and
configuration can still be maintained. The
ability to wake-up from an I/O source provides
the ability for the user or another device in the
system to wake the device up. Hibernate mode
can also be used to eliminate a power switch in
a handheld device (since the device can wakeup
on any button press).
A programmable SoC (PSoC) offer high levels
of integration and at the same time provides the
user the ability to build their own custom
peripherals using a highly configurable and
programmable system. Carefully designed programmable
SoCs can offer world-class power
management features that not only meet MCU
power numbers but also offer a configurable
power management system that can also deliver
precise analog performance. Cypress Semiconductor
PSoC 3 and PSoC 5 families are
field-programmable embedded SoCs that have
programmable digital blocks and configurable
analog blocks. These devices are designed to
offer utmost flexibility and programmability to
the user while consuming very low sleep and
active current. It also offers precise analog
performance (16-bit to 20-bit precision). PSoC
Creator is an integrated development environment
software that can be used to rapidly
develop designs for the PSoC 3 and PSoC 5
families from end to end – all the way from
device selection, configuring/programming the
digital and analog peripherals, configuring the
power system, firmware development, to debug
and programming. ■

Low-power FPGA solutions for
■ One of the most important benefits of the
digital era is that all communication media (e.g.
text, images, audio, video and animation) can
be represented in a format that is easily handled
by a microprocessor or digital logic. This
makes it possible to create multi-mediaenabled
devices that allow users to easily view
and interact with the application and related
digital media - anywhere and anytime. From
multi-function phones to automotive consoles
or even internet-enabled fridges, users are acquiring
the taste for being able to rapidly access
information and easily control their applications
through a multifunction graphical display.
As the cost of displays is constantly falling and
customers clearly have a strong preference for
graphical user interfaces, an increasingly wide
range of applications are being driven to add a
graphics capability to their feature set. This
means that the market base for graphically driven
products is spreading quickly and that there
is growing demand for many different display
form factors and features (e.g. display resolutions,
input device support and interface standards).
As there is great pressure on product
manufacturers to stay ahead of the competition
by improving the graphical quality, display
manufacturers are highly motivated to reduce
costs and develop better displays as quickly as
possible. However, the downside of this is a relatively
short lifetime for display components.
Traditionally, most microcontroller families
contain only a small number of members
(often only one or two) that can drive a graphics
LCD. This severely limits the choice of
processor device feature set available to the designer
and usually results in the design-in of a
particular device that is matched only to the
current design specification. This limits the capabilities
of the processor, graphics features and
display support. Two or three years after the release
of a product it is likely that the graphics
display being used will become obsolete, the
market will require a higher resolution/colour
depth display and the microcontroller chosen
originally will not be able to support the new
display requirement or additional features. As
the choice of graphics-enabled devices is limited,
upgrading the graphics capabilities usually
involves choosing a device that is based on
different processor architecture. This means
that the software has to be ported to the new
processor and on a graphics or multimediaenabled
device this is usually the largest part of
the work required.
The advent of low-cost and low-power FPGAs
has made it practical to create products that can
deliver an order of magnitude increase in flexibility
through the use of programmable logic.
Being able to change the hardware enables users
to upgrade their products, even after purchase,
but more importantly developers can
FPGAS,PLDS & ASICS
graphics applications featuring LCDs
By Stefano Zammattio, Altera
FPGAs can do more than just
provide a flexible interface for
the display and touchscreen,
they can support a complete
graphics/video system
completely eliminating the
requirement for a
graphics capability in the
external processor.
Figure 1. A high performance FPGA-based embedded system
with graphics accelerator and video support
create their next-generation products without
re-spinning the circuit boards, or spawn
multiple products from a single design. This is
particularly beneficial for products that use
LCDs or similar types of displays. Support for
any type of LCD interface and related input
device can be easily accomplished by modifying
the LCD and input controller interfaces that are
implemented in the FPGA logic.
However, the FPGA can do much more than
just provide a flexible interface for the display
and touchscreen, it can support a complete
graphics/video system completely eliminating
the requirement for a graphics capability in the
external processor. This allows the designer to
use any external processor from the whole family
range. In fact, the complete system can operate
using processors implemented entirely in
the FPGA logic (e.g. Altera Nios II processor).
Figure 1 shows a full-featured FPGA-based
graphics system that can be used as part of an
automotive or home multimedia centre. The
parallel processing capability of the FPGA
logic makes it easy to implement video and
graphics processing without requiring a heavyduty
processor or high clock speeds. Special
graphics processing features can be implemented
into the LCD controller or into a
graphics accelerator to deliver a whole range of
sophisticated graphical capabilities. IP modules
for graphical acceleration and video processing
31 November 2009

FPGAS,PLDS & ASICS
Figure 2. Examples of effects that benefit
greatly from hardware acceleration include
alpha blending and anti-aliasing..
are available commercially and can usually be
tailored to suit any application, but the important
thing is that this IP is delivered in a format
that allows the use of the Altera system-level
design tool, SOPC builder, a quick and easy way
to create or modify system designs. Examples of
effects that benefit greatly from hardware acceleration
include alpha blending, anti-aliasing,
drawing and filling of geometrical shapes, scaling
and colour conversion of graphical elements
and support for scaled fonts (figure 2). TES is
a company that supplies a range of graphics
hardware acceleration IP solutions, they even
offer a full-blown 3D graphics engine that can
render 2-3 million triangles per second.
Feature Logic Elements
(LEs)
Basic LCD controller 2 - 3 KLE
Multi-layer controller 4 - 5 KLE
with Alpha
Video Input with basic 2 - 3 KLE
processing
Hardware accelerator for 6 - 8 KLE
basic 2D functions
Full-featured 2D hardware 11 – 13 KLE
accelerator
Flash player 14 – 16 KLE
(Imagem Technologies)
3D graphics accelerator ~75 KLE
(TES)
Table 1. Example logic element requirements
for hardware support of graphics
Another advantage of an FPGA-based system is
the ability to easily add new and novel features
required by an application, for example all the
effects listed already can be added to a basic
graphics engine. Additionally, features that
would be difficult or nearly impossible using a
standard microcontroller can be easily added.
For example, multiple channels of streaming
video, picture in picture capability, multiple
display support, image enhancement, object
recognition, motion tracking, camera distortion
correction, noise filtering, and even support for
playing flash animation files. All these features
have been implemented on Altera FPGAs and
descriptions of them can be found on Altera or
partner websites. Table 1 lists some example
graphics IP components and the amount of
Cyclone III FPGA logic resource required to
implement each individual feature. A minimal
basic graphics system will fit into a Cyclone III
3C5 device (the smallest device in the family)
whereas a high performance system similar to
that shown in figure 1 will require a 3C16 device
or larger. Memory and DSP requirements
for a simple display are minimal but they do
increase as hardware-accelerated features are
added. Fortunately the ratio of DSP and
memory to logic in the Cyclone III family is
well-suitedtothesetypesofapplicationssothat
the amount of available on-chip memory and
DSP resources is usually not a problem.
A HDL graphical reference design that supports
multilayered imaging and video (with multiple
layers and video input similar to that shown in
figure 1) can be downloaded from the Altera
website and easily implemented on any board
that carries a graphical LCD display. However
if a slightly easier path to FPGA-based graphical
engine design is needed, ready-made reference
designs with the embedded evaluation and
embedded system development kits (figure 3)
are provided. These reference designs have
been built for fast implementation, easy modification,
and minimal support. The graphics/video
pipeline has been broken down into
logical segments and each implemented as a relatively
simple SOPC builder IP component.
This makes it very easy to customise the system
by re-configuring the components, modifying
component HDL, replacing a component with
a different one or adding new components like
a graphics acceleration engine or video
processing block. In order to support a different
display, changes to the LCD interface are
usually required; for example, the width of the
data bus interface, the screen aspect ratio, the
November 2009 32
Figure 3. The Nios II embedded evaluation kit (left) and embedded system development kit -
Cyclone III edition
timing signals for indicating the end of a horizontal
line, or the time taken to restart the line
drawing at the top of the screen may all need
modification. This is easily achieved by changing
the parameters of the video synch generator
IP component configuration window. This
figure also shows the SOPC system design for
the graphics pipeline used in these reference designs
– editing this system just requires a few
simple clicks of the mouse to re-configure, add,
or remove IP components. Most (if not all) of
the graphics IP providers deliver their IP as
SOPC builder components to take advantage of
the rapid development and ease of implementation
delivered by SOPC builder.
In figure 1 there are two types of connections –
memory-mapped (where there is an address
and a data bus) and streaming (where there is
a point-to-point connection between components).
Memory-mapped connections are wellsuited
to random access and multiple connections
between a master and several slaves.
Streaming connections are perfect for highspeed
connections between hardware blocks
that make up a processing pipeline. Fortunately
the SOPC builder tool supports both types of
connections and offers a range of adaptor
components that enables a mix of different
types of component and connections to be easily
used. This includes adaptors that change the
width and format of the streaming connection
to optimise the performance of the pipeline.
Streaming is particularly well suited to video
support and Altera offers an SOPC builder
compatible video IP suite to support video
input, clipping, scaling and conversion so that
video can be easily displayed as a background,
picture in picture, or full-screen display.
Finally, for many applications designing the
graphical interface software is what can actually
consume most of the development time/resource;
fortunately this can be alleviated by the
use of an appropriate graphical application developmenttoolset.ManyRTOSvendorsmarket
graphical libraries to facilitate software development
for graphics, but some tools go much
further than this. They can facilitate the transfer
of graphics from professional graphical tools

to the embedded platform, making it easier to
integrate and modify high quality images and
animations. They may also provide a PCbased
display emulator, so that the GUI can be
thoroughly tested and reviewed before even
going near the embedded platform. Once the
design is final, an automated code generator
createsalltheCcoderequiredtodrivethesys-
■ The number of FPGA designs that use embedded
microprocessors continues to grow. According
to Dataquest, there are approximately
100,000 FPGA design starts a year, of which
some 30% include a microprocessor of some
kind. There are several reasons for this trend.
First, data flow applications are more suitable
for programmable hardware, while an embedded
microprocessor is better suited to implement
control flow-based applications. Second,
an embedded processor provides more flexibility
when making design changes. Finally,
using an embedded microprocessor as a soft
core eliminates the risk of processor obsolescence.
Traditionally there have been limitations
associated with embedded FPGA microprocessors,
including cost as well as the speed
and performance of the design. With advances
in process technology and design techniques
these limitations are being overcome and designers
are now more likely to consider the use
of an embedded FPGA microprocessor in their
applications. Historically, off-the-shelf micro-
tem and manage the graphics. This auto-generated
code targets the API of the hardware
graphics engine so that any hardware optimisations
or changes do not require any application
software changes. The use of graphics resource
databases created by the tools and automated
code generation makes it very easy to
change the GUI functionality and appearance
processors have been significantly less expensive
than their embedded counterparts; however,
nowadays low-cost FPGAs are proving to be a
cost-effective solution. If a design already uses
an FPGA, the processor can be integrated into
the fabric of the existing FPGA, saving the cost
of a discrete device or a new FPGA. Design
cycle time is also an important criterion. How
quickly can the hardware associated with the
microprocessor sub-system be architected and
implemented? How long will it take to write,
test and debug the code that runs on the microprocessor?
Over the last few years, development
software for embedded microprocessors
has improved greatly in its overall functionality
and ease of use. As a result, a design can now
be running and tested in a matter of minutes.
Time-to-market is reduced because it is much
quicker and simpler to implement functionality
in software than in hardware. Performance
has historically been better using off-the-shelf
microprocessors. With improved technology,
however, FPGAs have advanced significantly in
FPGAS,PLDS & ASICS
(e.g. through the use of skins). Clearly the flexibility
of low-cost FPGAs like Altera Cyclone III
has a lot to offer the developer who wants to
add a scalable, flexible, and long-lifetime graphics
feature to their product. So next time you
watch the tear-down of a product that includes
a graphical display, do not be surprised if an
FPGA is found at the heart of the system! ■
Highly configurable embedded 32-bit
RISC processor for FPGA applications
By Alexander Hahn, Lattice
Off-the-shelf microprocessors
have traditionally given better
performance, but with
improved technology FPGAs
have become increasingly
competitive and embedded
processors are now attractive
in many designs. This article
demonstrates their advantages
by examining the
LatticeMico32.
A typical embedded RISC
processor sub-system
their feature sets and in overall system speeds.
With FPGAs now able to handle greater bandwidth,
embedded processors have become attractive
choices for many designs. Furthermore,
due to close interaction with other dedicated
blocks of the FPGA and the extensibility of a
soft IP core to provide a system interface, an onchip
processor can now provide a superior design
solution in terms of both performance and
throughput. The advantages of using an embedded
soft processor become clear when examining
a specific processor such as the LatticeMico32.
Let us look at a typical embedded
processor sub-system, for example the LatticeMico32
soft processor. The processor needs
some capabilities to communicate with the outside
world; therefore the core is typically connected
to an on-chip bus system, in this case a
Wishbone open source bus. Then there is the
need for a memory system, which holds the
program code of the processor, as well as the
data used by the processor core. For external
communications there may be a variety of
33 November 2009

FPGAS,PLDS & ASICS
Figure 2. LatticeMico32 – a configurable
RISC processor core
interfaces in a typical system, ranging from simple
communications interfaces and connections
to more complex protocols up to dedicated
hardware blocks in the application. The processor
bus architecture now needs to allow connections
both to peripherals and the memory
system. A typical system is illustrated in figure 1.
Let us look at the processor core itself. The LatticeMico32
is a RISC architecture microprocessor
based on Harvard-style bus organization
(figure 2). The RISC architecture provides
a simpler instruction set and faster performance.
The Harvard style bus architecture
provides separate instruction and data buses,
which enable single-cycle instruction execution.
The processor provides 32 general-purpose registers
and can handle up to 32 external inter-
Figure 3. Arbitration schemes
Figure 4: Creating a custom peripheral component
rupts. Customization of the processor allows insertion
of multiplier or barrel shifter as well as
different debug functionality. The Mico32 can
be targeted for various memory systems, using
inline memories both for instruction and data.
Inline memories can build up a native Harvard
architecture and allow single-cycle access to instructions
and data. For larger memory requirements,
the processor connects via an arbiter
to other memory modules or interfaces.
This can be based on on-chip memories implemented
in the memory resources of the
FPGA, or interfaces to external memories such
as SSRAM, flash or DRAM. Appropriate interface
modules handling all the access protocol to
the external memories are provided by the
MSB. Optional instruction and data caches are
available and can be configured with various
options (cache size, cache line size etc).
The processor connects to a wide variety of peripheral
components via an open source Wishbone
bus interface. A graphical user interface allows
easy and fast creation of processor platforms
for fast turnaround cycles. Besides standard
memory controllers this may include interfaces
not only for I²C, general purpose IOs,
timer, UART and SPI, but also more complex
modules such as a PCI interface or a TriSpeed
Ethernet MAC. A direct memory access (DMA)
November 2009 34
controller is available to add separate masters to
the Wishbone bus and unload the processor
from data transfer activities. This also allows
DMA-capable peripherals to efficiently transfer
their data directly into the memory system,
saving bandwidth on the on-chip bus.
In addition to the peripheral components and
DMA, the user can customize the arbitration
scheme. The bus structure generator supports
both master side and slave side bus arbitration.
Master side bus arbitration, if it can meet system
performance requirements, provides a
simple low cost solution. If there are multiple
bus masters and multiple slave blocks in a design,
master side bus arbitration restricts communication
to a single bus master at any one
time. In many designs, slave side arbitration improves
performance by allowing two or more
bus masters to communicate with separate slave
devices simultaneously. Figure 3 shows the
available arbitration schemes.
Users can also create their own Wishbone busbased
peripheral components, which then automatically
connect to the bus architecture via
their integration into the MSB. As a result, the
LatticeMico32 architecture provides two possibilities.
Firstly, one can create a custom component
and attach this to the list of available
components in the MSB (figure 4). Secondly,
one can create so-called Passthru components,
which can export a Wishbone-based peripheral
interface to the outside core, so the user can
add any arbitrary logic block from other parts
of the FPGA. These configuration options enable
customization of the LatticeMico32 for different
applications. The bandwidth ranges
from small and area-optimized controllers
with on- or off-chip memories to fully featured
platforms with multiple interfaces and access to
larger memory address ranges (possibly offchip).
Having access to other logic modules
from the FPGA also allows close interaction between
the processor system and the dedicated
modules of the FPGA for further performance
improvements. Traditional complex access
mechanisms using external controllers in parallel
to the FPGA are eliminated.
Because the processor code is readable Verilog
RTL code, the user can easily identify function
blocks of the IP, such as instruction fetch unit,
instruction decode or the ALU and the various
pipeline stages. Therefore those can also be
modified and enhanced by custom instructions.
A user can also implement opcode. The LatticeMico32
therefore provides a spare opcode
field in the instruction word. A custom instruction
can be created following some basic
steps: Enhance Instruction decoder. This is a
simple case function that extracts an internal
opcode and generates all the necessary control
signals required to integrate this command into

the LatticeMico32. Write functional implementation
and integrate this into the LatticeMico32
ALU. In case of multi-cycle commands,
create the necessary stall signals to
properly handle the processor pipeline. If other
dedicated logic is required (such as additional
special purpose registers), this can be added
separately to the core.
Extending the processor core by custom instructions
and adding custom peripherals is a
very powerful way to tailor the processor core
towards the performance requirements of the
system. Often, some dedicated functionality can
be implemented better in hardware than in
software. Or parallelism can gain additional
performance. Such mechanisms allow a seamless
integration of those hardware acceleration
modules into the processor architecture. This
maintains the capability to handle access to
these parts in the same fashion as normal software
code or the use of standard peripherals.
For applications requiring data/signal processing
capabilities, often a combination of RISC
processor functionality and DSP is required to
achieve system performance and throughput.
Adding extensions and custom components can
also include signal processing units. These can
be implemented very efficiently in hardware,
using dedicated DSP building blocks such as
multiply/accumulate, which are available in
hardware on a variety of FPGAs.
The LatticeMico32 System includes three integrated
tools. The MicoSystem Builder (MSB)
generates platform descriptions and the associated
hardware description language (HDL)
code for hardware implementation. Designers
can choose which peripheral components to attach
to the microprocessor, as well as specify the
connectivity between them. The C/C++ software
project environment (SPE) calls a compiler,
assembler and linker and enables the development
of code targeted to run on platforms
created with the MSB. It is through the C/C++
SPE that platforms created in MSB can be ref-
Configuration Family LUTs EBRs Frequency
vides the ability to debug in assembly and watch
the processor registers and memory. Designers
can also observe and control the execution of
the code in the physical hardware using the
Reveal logic analyzer. All tools and IP are fully
integrated into the ispLEVER FPGA software
design environment, which allows rapid design
creation through the entire FPGA design flow.
The tools also facilitate efficient use of available
FPGA resources. During the build process, the
processor code and its peripherals are created in
fully readable RTL Verilog source code. Scripts
for synthesis and simulation are provided, and
constraint files take care of the hardware settings
and pin-out. There are currently three operating
systems available: uClinux and U-Boot
from Theobroma Systems, μC/OS-II RTOS
from Micriμm and μITRON RTOS from Toppers/JSP.
The processor core is provided with an open
source licence. The Lattice open IP core licence
agreementwillbeusedwiththeHDLcodethat
is generated by the MSB tool. Most of the
graphical user interfaces will be licensed under
an Eclipse licence, while for the internal workings
of the software, such as the compiler, assembler,
linker and debugger, the licensing
scheme will follow the GNU-GPL. Because this
is open source soft IP, the processor IP core can
also be migrated free of charge to other
technologies and implementations.
The processor provides high performance as
well as minimal resource utilization. For designers
who are concerned about resources, the
basicconfigurationusesnoinstructionordata
cache, a single-cycle shifter and no multiplier.
For those concerned more with performance,
the full configuration uses 8k bytes of instruction
cache, 8k bytes of data cache, a 3-cycle
shifter and a multiplier. For users who need a
compromise, the standard configuration is
similar to the full configuration, but without
the 8k bytes of data cache. Table 1 shows
resource utilization and performance for the
LatticeECP3 FPGAs. ■
Basic ECP3 1835 0 112 MHz Includes barrel shifter, no
MULT,
no Caches
Standard ECP3 2189 5 119 MHz Includes barrel shifter, 32
bit MULT, 8k bytes
I-$, no D-Cache
Full ECP3 2435 10 116 MHz Includes barrel shifter, 32
bit MULT,8 k bytes
I-$, 8 k bytes D-$
erenced. Table 1: The LatticeMico32 C/C++ source resource code debugger utilizationpro and performance using LatticeECP3
FPGAS,PLDS & ASICS
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Jürgen Hübner
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35 November 2009

PRODUCT NEWS
■ ST: ZigBee platform for remote motion
control
STMicroelectronics has introduced Motion-
Bee, a complete, ready-for-use platform that
combines motion sensing with ZigBee wireless
technology in a single ultra-compact module.
Boasting low power consumption and high level
of integration, ST’s MotionBee enables system
developers to quickly and cost-effectively build
wireless sensor networks for remote motion
recognition and tracking in many different application
areas, including healthcare, security, industrial
control and environmental monitoring.
News ID 509
■ Digi launches fleet management telematics
devices
Digi International introduces the ConnectPort
X5 family of compact, ruggedised telematics devices
with optional satellite functionality incorporating
cellular, satellite, GPS, Wi-Fi and
vehicle area network wireless technology in one
device. The ConnectPort X5 family is tailored
specifically for the demands of fleet management
applications.
News ID 537
■ Altium: FPGA-based development
board with royalty-free IP
Altium has launched a new addition to its
NanoBoard family of FPGA-based development
boards. The NanoBoard 3000 is a programmable
design environment, supplied complete
with hardware, software, ready-to-use,
royalty-free IP and a dedicated Altium Designer
Soft Design license. Designers have everything
they need to explore FPGAs "out of the
box ". They are no longer forced to search the
web for drivers, peripherals or other software,
and then have the hard work of integrating all
these elements to make them work together.
News ID 448
■ Atlantik: improved security in public
short-distance traffic
Atlantik Elektronik offers solutions for video
transmission to improve the security in the
local public transport system. Especially the integration
of video systems in an extensive security
concept is very successful. Although 50
percent of Munich’s interurban trains are
equipped with video surveillance systems, this
could not prevent the assault of a 50 years old
entrepreneur.
News ID 467
November 2009
■ CMX: TCP/IP stack with a variety of
add-on options
CMX Systems offers the CMX-MicroNet
TCP/IP stack with a variety of Add-On options
for most 8-, 16-, and 32-bit microcomputers,
microprocessors and DSP's. CMX-MicroNet is
a TCP/IP stack specially crafted to work with
virtually all processors and features an extremely
small ROM requirement ranging from
5K to 28K and very minimal RAM requirements
of about 500 bytes plus buffers for
packets.
News ID 526
■ PEAK-System enhances CAN monitor
for Windows
PEAK-System Technik has released version 5 of
their PCAN-Explorer for Windows. The
PCAN-Explorer is a universal monitoring software
for displaying data traffic on CAN networks.
For a simple and clear allocation of the
individual messages, these can be identified as
so-called symbols. The VBScript implementation
allows the creation of macros to automate
complex tasks.
News ID 566
■ Artisan: major new version of model-driven
development tool
Artisan Software Tools has launched a major
new version of its model-driven development
tool suite, Artisan Studio Version 7.1 delivering
new modeling features including support for
the OMG Unified Profile for DoDAF and
MODAF standard, improved model diagram
presentation through glossUML, all new documentation
generation through Artisan Publisher,
increased extra-large model support
and enhanced UML Activity modeling.
News ID 567
■ XMOS and Digi-Key announce global
distribution agreement
XMOS announces a global distribution agreement
with Digi-Key. XMOS' complete range of
event-driven processors and development
boards are in stock and ready to ship from Digi-
Key. This includes XMOS' new XS1-L1chip targeted
at the mass electronics market . The XS1-
L family provides embedded software developers
with an energy-efficient, scalable, multi-core
solution which enables them to build complete
systems combining interface, DSP and control
functions entirely in software.
News ID 458
36
■ MSC: 32-bit processors with integrated
single/dual e600 core
Two new processors from e2v, available at
MSC, offer the high-performance e600 core for
demanding applications including aerospace
anddefence,networkingaswellasstorageand
wireless infrastructure. The PC8640(D) features
single or dual e600 cores running at up to 1250
MHz. The PC8641(D) is equipped with single
or dual e600 cores running at up to 1500 MHz,
operating over a market leading extended temperature
range of -55 to + 125 C.
News ID 617
■ ARM: Cortex-A5 processor scales from
handsets to lifestyle internet devices
ARM launches the ARM Cortex-A5 MPCore
processor, a small, low power ARM multicore
processor capable of delivering the Internet to a
wide range of devices, from ultra low cost handsets,
feature phones and smart mobile devices,
to pervasive embedded, consumer and industrial
devices. The Cortex-A5 uniprocessor provides
a migration path for ARM926EJ-S and
ARM1176JZ-S processor licensees.
News ID 627
■ Atmel: megaAVR picoPower MCU
with 128 KB of Flash
Atmel announces the availability of a 128 KB
picoPower megaAVR microcontroller, targeting
size-constrained, low-power applications. The
small 44-pin package makes the ATmega1284P
ideal for applications such as wireless and ethernet
nodes, home automation and other codeintensive
battery or signal-line powered products,
combined with its ultra-low-power consumption,
128 KB of flash and 16 KB RAM.
News ID 521
■ Cypress to highlight new PSoC 3
architecture at X-Fest
Cypress will partner with Avnet for the X-Fest
global series of free technical seminars to be
held in 37 locations around the world from October
2009 through February 2010. Cypress will
demonstrateitsnewlyannouncedPSoC3programmable
system-on-chip architecture. The
new PSoC architectures dramatically increase
performance and extend the world’s only programmable
analog and digital embedded design
platform, delivering unmatched time-tomarket,
integration, and flexibility across 8-, 16-
, and 32-bit applications.
News ID 514

■ The Debug Store: Gold Distributor for
Xeltek in Europe
Xeltek has appointed The Debug Store as its
first Gold Distributor in Europe. The Gold Distributor
is committed to keeping Xeltek programmers
and popular adapters in stock so customers
have fast access to products. It also offers
detailed advice about the suitability of a
programmer and associated adapter for programming
the customer’s devices. If the customer
also needs to minimise downtime should
his programmer fail, an extended warranty
service is also available, providing a loan unit,
delivered the following working day.
News ID 619
■ Xilinx: FPGAs compliant with
PCI Express 1.1 spec
Xilinx announces that its Spartan-6 FPGA
family is compliant with the PCI Express 1.1
specification, enabling low-cost implementation
of serial connectivity solutions for consumer,
automotive, wireless, and other pricesensitive
or high volume markets such as in-vehicle
infotainment, flat-panel displays, and
video surveillance. PCIe 1.1 is implemented in
Spartan-6 LXT devices with Xilinx GTP serial
transceivers capable of up to 3.125Gbps and the
LogiCORE solution using the integrated Endpoint
block for PCI Express. The GTP serial
transceivers are fully characterized across
process, voltage, and temperature.
News ID 540
■ Toshiba: USB 2.0 dual single pole double
throw bus switch
Toshiba Electronics Europe has expanded its
family of ultra-high-speed CMOS interface ICs
with a miniature, low-power CMOS switch IC.
The TC7USB221 is a USB 2.0 dual single pole
double throw bus switch with low ON resistance
and low pin capacitance for Hi-Speed USB
operation with data rates up to 480Mbps. A
typical application for the IC would be a multiplexer/demultiplexer
function between two
USB controllers.
News ID 613
■ Infineon: launch of European Technology
Cooperation ‘E3Car’
A large European research project to advance
the development of electric vehicles has been
launched under the leadership of Infineon.
The E3Car (Energy Efficient Electrical Car)
project brings together 33 automotive companies,
key suppliers, and research facilities
from a total of eleven countries to collaborate
on boosting the efficiency of electrically-driven
vehicles by more than one-third.
News ID 585
■ Tensilica: dataplane processor core
for deeply Embedded control
Tensilica introduces the Xtensa 8 customizable processor,
the eighth generation of its low-power dataplane
processor cores. The Xtensa 8 processor 32-bit architecture
core starts at a size of just 15,000 gates, consuming
less than 0.05mm2 in 40nm process technology
with power dissipation starting at 12
μW/MHz.Designers using an Xtensa 8 DPU can select
from an expanded library of pre-verified configuration
options to get the exact functionality they need.
News ID 609
■ Microchip: metering analogue front-end
samples with up to 64ksps
Microchip announces its next-generation Analogue
Front End for metering applications. The
MCP3901 AFE features high-accuracy, dual 16-
/24-bit Delta-Sigma ADCs with up to 91dB Signal
to Noise and Distortion; internal Programmable
Gain Amplifiers and voltage reference;
phase-delay compensation; and a modulator
output block, enabling more precise
measurements than competitive solutions.
News ID 574
■ Altium and Premier Farnell announce
distribution agreement
Altium has appointed Premier Farnell as the
web distributor for its new NanoBoard 3000
FPGA-based development board. The agreement
extends to Premier Farnell’s family of
global marketing and distribution services.
News ID 454
37
PRODUCT NEWS
■ NI: programmable FPGA to provide
intelligent distributed nodes
National Instruments announces new FPGA
capabilities for the NI 9144 expansion chassis.
By downloading the NI-Industrial Communications
for EtherCAT 1.1 driver, engineers can
now run National Instruments LabVIEW
FPGA code directly on the NI 9144 chassis to
execute custom triggering, inline processing
and control within an application.
News ID 588
■ TI: RF4CE development platform for remote
control applications
Texas Instruments, C.G. Development and
Quanta Microsystems announce a complete,
easy-to-use RF4CE development platform for
advanced RF remote control applications. This
development platform is based on TI’s latest
IEEE 802.15.4 chipset, CC2530, along with TI’s
MSP430 MCUs and related software stacks supporting
ZigBee PRO and ZigBee RF4CE.
News ID 559
■ STM: 8-bit MCUs with ultra-low-power
technology
STMicroelectronics has begun volume production
of the first microcontrollers to combine
its high-performance 8-bit architecture with the
company’s recently announced ultra-low-power
innovations to save power in active modes as
well as when idle. The STM8L product family
comprises 26 devices in three lines spanning a
broad spectrum of performance and function.
News ID 441
■ Xilinx and ARM: development collaboration
Xilinx and ARM collaborate to enable ARM
processor and interconnect technology on Xilinx
FPGAs. Xilinx is adopting ARM Cortex processor
IP, using performance-optimized ARM cell libraries
and embedded memories for their future
programmable platforms. In addition, ARM and
Xilinx are working to define the next-generation
ARM AMBA interconnect technology that is enhanced
and optimized for FPGA architectures.
News ID 608
November 2009

PRODUCT NEWS
■ Actel: real-time firmware access and
updates for low-power FPGAs
Actel has released its new Firmware Catalogue.
This new tool streamlines the locating and generating
of firmware that is compatible with Intellectual
Property cores used in Actel embedded
processor based low-power IGLOO, ProA-
SIC3 or Fusion mixed-signal FPGA designs.
The Firmware Catalogue is a standalone executable
program that enables the browsing, selection,
and GUI configuration of firmware
drivers, hardware abstraction layers and design
examples.
News ID 496
■ Xilinx: design suite supports high
bandwidth Virtex-6 HXT FPGAs
Xilinx announces design support for Virtex-6
HXT FPGAs with the 11.3 release of the ISE Design
Suite software. Optimized for 40G/100G
wired telecommunications and data communications,
Virtex-6 HXT FPGAs deliver serial interface
technology to designers of ultra-high bandwidth
systems with line rates in excess of 11 Gbps.
News ID 459
■ TI: 200-mA linear regulators with auto
low-power mode
Texas Instruments introduces a family of 200mA,
low dropout regulators. Auto low-power
mode allows the TPS727xx to achieve less
than 8 uA without an additional mode pin and
automatically switches to and from low power
depending on load current.
News ID 528
■ ADI: supervisory circuits extend battery
life in mobile applications
Analog Devices expands its portfolio of supervisory
ICs with new microprocessor supervisory
circuits for monitoring under-voltage
conditions in handheld industrial instruments,
telecommunications devices, and other portable
applications. The ADM6326, ADM6328,
ADM6346 and ADM6348 supervisory circuits
feature an ultra-low 500-nA supply current that
can extend the battery life of mobile devices.
News ID 439
November 2009
■ NatSemi: wireless basestation IF sampling
reference design
National Semiconductor announces the availability
of an intermediate frequency sampling
receiver reference design for multi-carrier,
multi-standard wireless basestations addressing
GSM/EDGE, WCDMA, LTE and WiMAX standards.
The subsystem reference design kit includes
reference design board, software,
schematic, bill of materials and Gerber files.
News ID 607
■ Renesas: 200 MHz SuperH MCU
with 3,75MB Flash
Renesas announces the SH72546R SuperH
family microcontroller designed for use in automotive
engine and transmission control systems.
The device combines high-speed operation
of up to 200 MHz with flash memory capacity
of 3.75 MB.
News ID 598
■ MSC: high temperature voltage control
crystal oscillator
MSC offers Vectron’s high temperature voltage
control crystal oscillator VX-400 product platform
for extreme environment applications.
These include oil and gas exploration markets,
industrial process control as well as military and
aerospace applications. Specifically designed for
operation in such harsh environment applications,
the VX-400 leverages an unique crystal
resonator mounting, as well as its substrate and
component attachment schemes to ensure reliable
component performance under shock
and vibration.
News ID 444
■ Maxim: 8x8 keypad controller
with 8 GPIOs/LED drivers
Maxim Integrated Products introduces the
MAX7360, a key-switch controller featuring multiple
key press/release detection on up to 64 keys,
plus 8 extra GPIOs/LED drivers and advanced
ESD protection. Individual key codes for each
press and release are stored in a FIFO register to
enable monitoring of multiple key-switch events.
News ID 612
38
■ Atlantik: 32-bit stereo DAC for high-end
digital audio devices
Atlantik Elektronik presents the AK4480, a 32bit
stereo DAC with an advanced architecture
enabling higher quality sound for professional
and high-end digital audio devices. The
AK4480 has three different digital filters: a 32bit
short delay filter which is suitable for
acoustic sounds, a 32-bit sharp roll-off filter for
traditional sounds, and a 32-bit slow roll-off filter
for a soft sound expression.
News ID 601
■ SiLabs: low jitter clock generator
for broadcast video applications
Silicon Laboratories introduces the expansion of
its Any-Rate Precision Clock family with the
Si5324 low jitter, most highly integrated clock IC
optimized for professional broadcast video applications.
The Si5324 replaces traditional multicomponent
video PLL solutions with a single
clock IC delivering jitter performance of 5 ps pkpk,
providing significant margin to all existing
and emerging video standards including 3G-SDI.
News ID 442
Advertisers Index
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ARM Germany 23
Digi-Key 2/39
Express Logic 7
Green Hills Software 5
HCC-Embedded 40
Hitex 25
Mentor Graphics 15
MSC 3
PEAK-System-Technik 17
Rutronik 21
Toshiba Electronics Europe 27

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