Intel’s Next Generation Microarchitecture Code Name Skylake

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AGENDAIntroduction and OverviewCore MicroarchitectureInterconnect and MemoryPower and ThermalOther IPs and TechnologiesChipset HighlightsOverclockingSummary and Q&AIntel Next Generation Microarchitecture Code Name Skylake
Next Generation Cache and Memory Solutions• Double throughput of the last level cache (LLC) miss handling• Fabric throughput was doubled without scarifying power• New eDRAM cache architecture, more products with eDRAM• Support of faster DDR memory• Main memory security and integrity engine- Used for Intel® Software Guard Extension (Intel® SGX) and other securitycriticaldata• Improved memory QoS for high resolution displays and integratedimage signal processor (ISP)25Intel Next Generation Microarchitecture Code Name Skylake
Page 1 and 2: Technology Insight:Intel’s Next G
Page 3 and 4: AGENDAIntroduction and OverviewCore
Page 5 and 6: Skylake Development AdventureStart3
Page 7 and 8: Intel’s Skylake Microarchitecture
Page 19 and 20: SKL Core Microarchitecture at a Gla
Page 21 and 22: Instruction Window Keeps Increasing
Page 23: Power Optimizations in the SKL Core
Page 27 and 28: eDRAM Based CacheL1L2CoreL1 DL2L1 I
Page 29 and 30: eDRAM as Memory Side Cache• Obser
Page 31 and 32: Power ReductionSame process as Broa
Page 33 and 34: Voltage and Thermal Optimizations
Page 35 and 36: Integrated ImageSignal ProcessorInt
Page 37 and 38: Skylake ISP Advanced CapabilitiesHD
Page 39 and 40: Intel® Software Guard Extensions (
Page 45 and 46: Extreme Overclocking AchievementsAc
Page 47 and 48: Summary and Next Steps• The new S
Page 49 and 50: Other Technical SessionsSession ID

Intel’s Next Generation Microarchitecture Code Name Skylake

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