A clocking technique for FPGA pipelined designs

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690 O. Cadenas, G. Megson / Journal of Systems Architecture 50 (2004) 687–696RequestAcknowledgeCDelayCCDelayCRequestAcknowledgeR1R2DelayMS-CTRLMS-CTRLA2A1 Lm Ls Lm LsDelayData InRegisterLogicRegisterLogicData OutData InM-regS-regLogicM-regS-regLogicData outFig. 2. Left: A two-stages four-phase micropipeline. Right: DLAP pipelining for two-stages.3.1. General scheme of PP-pipelineThe PP-pipeline is basically a representation ofthe micropipelinig state rule specified as a statemachine. Fig. 3 shows a PP-pipeline control forthree stages, where the U i (or PP-modules) correspondto state machines controlled by a globalclock signal clk. The processing time associatedwith pipeline stages is modelled by delay lines;these are shown on top of each PP-module. Registersof a pipelined datapath are clocked by locallogic i-1Delayclklogic iDelaydone i-1 done doneU ii+1i-1 U i U i+1go i-1go i go i+1p i-1p i p i+1Fig. 3. PP-pipeline control for three stages pipeline.pulses p i , generated by individual PP-modules. Atstage i, module U i generates synchronously p i onlyif both go i and done i are asserted. After processingat stage i 1 (modelled by delay i 1 ) done i will beactive (asynchronously) indicating that data isready to be delivered to stage i. Similarly go i whenasserted means that stage i þ 1 has accepted thedata from stage i. U i synchronizes these twoevents, at the first clock-edge after both signals areasserted U i will generate a clock pulse on p i . All thestages operate in parallel, accordingly the organizationof interconnected PP-modules is referred toas a PP-controller. In synchronizing signals doneand go, the PP-controller can be susceptible tometastable behavior [17]. We address this shortlybut first consider the circuit operation.Circuit operation: An Algorithmic State MachineChart (ASM chart) description and a circuitfor an individual PP-module is shown in Fig. 4.External events done and go are synchronized intodone:sync and go sync, respectively. The statemachine has two states: FIND and WAIT. FINDchecks the condition capt ¼ done i sync ANDFIND0doneiDQdone.syncWAITcaptTpcaptF1FTgoiclkresetFF0RD QFF1Rgo.syncD QFF2Rpgoii-1Fig. 4. An individual PP-module. Left: ASM chart specification. Right: A circuit implementation.
O. Cadenas, G. Megson / Journal of Systems Architecture 50 (2004) 687–696 691NOT(go i sync). The WAIT state loops until captis false and a single pulse (of a clock periodduration) is generated at p i . A PP-controller ofany number of stages requires initial conditions tothe leftmost done and the rightmost go signals.These initial states are set to high and low,respectively.As an illustration, consider the case in Fig. 3when done i 1 and go iþ1 are forced high and low,respectively. From analysis of the circuit in Fig. 4,after a master reset, all the go signals go low andafter the first clock edge a single pulse is generatedonly at p i 1 . The low-asserted level for go signalswas chosen to make this operation simpler after amaster reset. After the processing time at stageU i 1 (delay i 1 ), done i goes high and it is synchronizedby U i (one clock edge). At the next clockedge (second one), a single pulse p i is generated(for stage i to capture data from stage i 1). Aftergo i 1 is synchronized and returns to low, stage U i 1could capture new data. Taking go signals fromcapt instead of from p is like predicting the nextstagecapturing and go i 1 occurs simultaneouslywith p i thus saving one clock cycle in the PP-controlleroperation. A p i event, in turn, triggers thedelay element to generate done iþ1 and the operationis repeated. Different timing behaviors canresult based on the relatives values of delay i 1 anddelay i . The worst case is when delay i 1 > delay i ,and the pipelining runs at a period T pipe ¼ðbdelay i 1 =T clk cþ3ÞT clk where T clk is the clockperiod of the frequency f at which the state machineruns. This is illustrated in Fig. 5 for the caseof three interconnected PP-modules. The waveformsare generated when delay i 1 ¼ 23 ns anddelay i ¼ 7 ns, respectively. It is observed that thepipeline runs at a period of T pipe ¼ 5T clk as predictedby the formula given above.Returning to possible metastable problemsmight arise when synchronizing done and go signals,observe that these can be avoided by eliminatingthe flip-flop to synchronize go (flip-flop FF1in Fig. 4) and driving go i directly from go i 1 of thesubsequent PP-module. In fact, the risk of synchronizinggo is essentially the risk of synchronizingdone since go i 1 is a function of done:sync.The risk associated to done synchronization can beclosely studied based on design and technologyparameters of reliable synchronizer designs [17].For practical cases, the delay lines can be safelyreplaced with a synchronous counter. This issuitable for one of the applications described inSection 4.3.2. PP-pipeline with no delay linesPP-modules can be further simplified byremoving the delay lines shown in Fig. 3. Thissimplified version also eliminates the flip-flop tosynchronize go. Essentially done i is directly takenfrom p i 1 and the PP-controller is acting as a gatedclock [1]. The global clock is distributed to pipelinereset10 nsclkppi-1i23 ns7 ns50 nspi+1doneidonei+1Fig. 5. Simulation waveforms with no associated processing logic when delay i 1 ¼ 23 ns and delay i ¼ 7 ns for the case of threeinterconnected PP-modules.
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