HCI / NBTI - Celestry Design Technologies, Inc.
HCI / NBTI - Celestry Design Technologies, Inc. HCI / NBTI - Celestry Design Technologies, Inc.
RelXpert 1 What is Hot-Carrier Injection (HCI) Induced Degradation and Why Does it Slow Your Design Down? With designs moving into deep submicron (DSM) levels, shorter channel lengths cause the electric field in the channel to become larger. This causes more electrons to become energetic or "hot". Some of these hot electrons will damage the channel-oxide interface and lead to circuit performance degradation. Using the device centric LDD structure to alleviate hot-carrier injection (HCI) damage will lower the device current driving capability, and consequently circuit performance. Trade-offs between HCI design rules and performance become increasingly complex as technology moves further into DSM levels. These overly conservative HCI design rules are a roadblock in the push for high-performance design that must be removed. What is Negative Bias Temperature Instability (NBTI) Degradation and Why Does it Cause Immediate Failure? A high vertical electrical field at a high temperature for tox < 50 Augstroms causes negative bias temperature instability (NBTI). This makes the circuit fail immediately-you do not have to wait ten years for lower product yield significantly at burn-in. The major damaging mechanism is the hole trapping and interface state generation. Positive bias temperature instability (PBTI) is less significant. NBTI has become a major concern for reliable integrated CMOS devices because of the threshold voltage (Vth) shift of p-MOSFET, Idsat reduction, and 1/f noise for the DSM CMOS semiconductor industry. "With Celestry's products we can design more aggressively in our 0.13um CMOS and BICMOS processes, and obtain higher performance and better density products for our Computer Peripherals and Consumer markets, while at the same time not compromising yield and long-term reliability." -- STMicroelectronics
Celestry's Reliability Solutions RelPro+ TM and BSIMPro+ TM allow the designer to generate HCI and NBTI AgeMOS TM SPICE models for circuit simulation that factors in reliability. RelXpert TM allows designers and technology developers to reduce performance stealing design margins by accurately simulating HCI and NBTI degradation under realistic circuit operating conditions. RelXpert is the rule generator and design checker you have been waiting for! The result is an optimized design that delivers: ◆ best possible performance ◆ improved yield ◆ reliable operation Additionally, for today's largest designs, UltraSim TM , a high-performance hierarchical circuit simulator, provides full-chip transistor-level reliability simulations UltraSim gives the designer real-time simulation capability: ◆ Built-in support for HCI and NBTI simulations ◆ Full-chip view of HCI effects on timing HCI / NBTI Simulation is the Path to Higher Performance Without accurate HCI and NBTI simulations, you can only approximate the circuit degradation, and will result either in excessive design margins, or design failure. Correct HCI and NBTI simulation allows you to accurately predict a circuit's degradation over time, enabling you to create a faster design without sacrifice of reliability. Furthermore, guard banding (or product binning) during product test will also be more accurate. ◆ The result is a faster chip with better HCI and NBTI reliability. Calculate the Degradation of Each Transistor Simply provide the SPICE netlist, Isub and Igate parameters, and one of the following reliability model options: ◆ Degraded SPICE model parameters* ◆ AgeMOS model parameters** RelXpert and UltraSim will use the results of SPICE simulations in its calculation of the individual device degradation, and optionally overall circuit degradation, for a user-specified number of years. It's like getting a sneak preview at your circuit's future performance. *Can be obtained from BSIMProTM or BSIMPro+. ** Can be obtained from BSIMPro+ Contact Celestry Design Technologies, Inc. for details. RelXpert 2
- Page 1: RelXpert The Solution for Circuit-L
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RelXpert<br />
1<br />
What is Hot-Carrier Injection (<strong>HCI</strong>) Induced<br />
Degradation and Why Does it Slow Your <strong>Design</strong> Down?<br />
With designs moving into deep submicron (DSM) levels, shorter channel lengths cause the<br />
electric field in the channel to become larger. This causes more electrons to become<br />
energetic or "hot". Some of these hot electrons will damage the channel-oxide interface<br />
and lead to circuit performance degradation.<br />
Using the device centric LDD structure<br />
to alleviate hot-carrier injection (<strong>HCI</strong>)<br />
damage will lower the device current<br />
driving capability, and consequently<br />
circuit performance. Trade-offs<br />
between <strong>HCI</strong> design rules and<br />
performance become increasingly<br />
complex as technology moves<br />
further into DSM levels. These<br />
overly conservative <strong>HCI</strong> design<br />
rules are a roadblock in the push<br />
for high-performance design that<br />
must be removed.<br />
What is Negative Bias Temperature Instability (<strong>NBTI</strong>)<br />
Degradation and Why Does it Cause Immediate Failure?<br />
A high vertical electrical field at a high<br />
temperature for tox < 50 Augstroms<br />
causes negative bias temperature<br />
instability (<strong>NBTI</strong>). This makes the circuit<br />
fail immediately-you do not have to wait<br />
ten years for lower product yield<br />
significantly at burn-in. The major<br />
damaging mechanism is the hole trapping<br />
and interface state generation. Positive<br />
bias temperature instability (PBTI) is less<br />
significant. <strong>NBTI</strong> has become a major<br />
concern for reliable integrated CMOS<br />
devices because of the threshold voltage<br />
(Vth) shift of p-MOSFET, Idsat reduction,<br />
and 1/f noise for the DSM CMOS<br />
semiconductor industry.<br />
"With <strong>Celestry</strong>'s products we can design more aggressively in our 0.13um CMOS<br />
and BICMOS processes, and obtain higher performance and better density<br />
products for our Computer Peripherals and Consumer markets, while at the<br />
same time not compromising yield and long-term reliability."<br />
-- STMicroelectronics
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