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HCI / NBTI - Celestry Design Technologies, Inc.

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RelXpert<br />

The Solution for Circuit-Level,<br />

Hot-Carrier / <strong>NBTI</strong> Simulation<br />

RelXpert TM allows designers<br />

and technology developers to<br />

optimize their designs for the<br />

best possible performance &<br />

yield without sacrificing reliability.<br />

Id (A)<br />

0.012<br />

( V )<br />

0.01<br />

0.007<br />

0.005<br />

0.002<br />

3.0<br />

2.0<br />

1.0<br />

: /out<br />

: /out<br />

<strong>HCI</strong> / <strong>NBTI</strong><br />

Plot Data nmos.pre<br />

nmos.pos<br />

Transient Response<br />

Fresh<br />

Degraded<br />

0.0 0.0 1.0 2.0 3.0 4.0 5.0<br />

Vd (V)<br />

0.0<br />

--1.0<br />

0.0 5.0n<br />

time ( s )<br />

10n<br />

Fresh<br />

Optimize Yield<br />

Aged


RelXpert<br />

1<br />

What is Hot-Carrier Injection (<strong>HCI</strong>) Induced<br />

Degradation and Why Does it Slow Your <strong>Design</strong> Down?<br />

With designs moving into deep submicron (DSM) levels, shorter channel lengths cause the<br />

electric field in the channel to become larger. This causes more electrons to become<br />

energetic or "hot". Some of these hot electrons will damage the channel-oxide interface<br />

and lead to circuit performance degradation.<br />

Using the device centric LDD structure<br />

to alleviate hot-carrier injection (<strong>HCI</strong>)<br />

damage will lower the device current<br />

driving capability, and consequently<br />

circuit performance. Trade-offs<br />

between <strong>HCI</strong> design rules and<br />

performance become increasingly<br />

complex as technology moves<br />

further into DSM levels. These<br />

overly conservative <strong>HCI</strong> design<br />

rules are a roadblock in the push<br />

for high-performance design that<br />

must be removed.<br />

What is Negative Bias Temperature Instability (<strong>NBTI</strong>)<br />

Degradation and Why Does it Cause Immediate Failure?<br />

A high vertical electrical field at a high<br />

temperature for tox < 50 Augstroms<br />

causes negative bias temperature<br />

instability (<strong>NBTI</strong>). This makes the circuit<br />

fail immediately-you do not have to wait<br />

ten years for lower product yield<br />

significantly at burn-in. The major<br />

damaging mechanism is the hole trapping<br />

and interface state generation. Positive<br />

bias temperature instability (PBTI) is less<br />

significant. <strong>NBTI</strong> has become a major<br />

concern for reliable integrated CMOS<br />

devices because of the threshold voltage<br />

(Vth) shift of p-MOSFET, Idsat reduction,<br />

and 1/f noise for the DSM CMOS<br />

semiconductor industry.<br />

"With <strong>Celestry</strong>'s products we can design more aggressively in our 0.13um CMOS<br />

and BICMOS processes, and obtain higher performance and better density<br />

products for our Computer Peripherals and Consumer markets, while at the<br />

same time not compromising yield and long-term reliability."<br />

-- STMicroelectronics


<strong>Celestry</strong>'s Reliability Solutions<br />

RelPro+ TM and BSIMPro+ TM allow the designer to generate <strong>HCI</strong> and <strong>NBTI</strong> AgeMOS TM SPICE<br />

models for circuit simulation that factors in reliability. RelXpert TM allows designers and<br />

technology developers to reduce performance stealing design margins by accurately simulating<br />

<strong>HCI</strong> and <strong>NBTI</strong> degradation under realistic circuit operating conditions. RelXpert is the rule<br />

generator and design checker you have been waiting for! The result is an optimized design that<br />

delivers:<br />

◆ best possible performance<br />

◆ improved yield<br />

◆ reliable operation<br />

Additionally, for today's largest designs, UltraSim TM , a high-performance hierarchical circuit<br />

simulator, provides full-chip transistor-level reliability simulations UltraSim gives the designer<br />

real-time simulation capability:<br />

◆ Built-in support for <strong>HCI</strong> and <strong>NBTI</strong> simulations<br />

◆ Full-chip view of <strong>HCI</strong> effects on timing<br />

<strong>HCI</strong> / <strong>NBTI</strong> Simulation is the<br />

Path to Higher Performance<br />

Without accurate <strong>HCI</strong> and <strong>NBTI</strong> simulations, you can only approximate the circuit<br />

degradation, and will result either in excessive design margins, or design failure.<br />

Correct <strong>HCI</strong> and <strong>NBTI</strong> simulation allows you to accurately predict a circuit's<br />

degradation over time, enabling you to create a faster design without sacrifice of<br />

reliability. Furthermore, guard banding (or product binning) during product test will also<br />

be more accurate.<br />

◆ The result is a faster chip with better <strong>HCI</strong> and <strong>NBTI</strong> reliability.<br />

Calculate the Degradation of Each Transistor<br />

Simply provide the SPICE netlist, Isub and Igate parameters, and one of the following<br />

reliability model options:<br />

◆ Degraded SPICE model parameters*<br />

◆ AgeMOS model parameters**<br />

RelXpert and UltraSim will use the results of SPICE simulations in its calculation of the<br />

individual device degradation, and optionally overall circuit degradation, for a user-specified<br />

number of years. It's like getting a sneak preview at your circuit's future performance.<br />

*Can be obtained from BSIMProTM or BSIMPro+.<br />

** Can be obtained from BSIMPro+<br />

Contact <strong>Celestry</strong> <strong>Design</strong> <strong>Technologies</strong>, <strong>Inc</strong>. for details.<br />

RelXpert<br />

2


RelXpert<br />

3<br />

Three Easy Steps to Faster <strong>Design</strong>s<br />

Step 1: Degradation Calculation<br />

How it works:<br />

1. Calculate actual current waveforms from real circuit operating conditions.<br />

2. Use these waveforms to calculate the "age" for each transistor. Lifetimes and percent<br />

degradation can then be made (see figure below).<br />

"We selected <strong>Celestry</strong> because of their<br />

experience in reliability analysis and<br />

unique 'hands-on' knowledge of deep<br />

submicron silicon issues. <strong>Celestry</strong>'s<br />

products will aide TI in more aggressive<br />

design shrinks and in reducing wasted<br />

performance and silicon lost by overly<br />

pessimistic design guardbands,"<br />

-- TI<br />

Lifetime (Years)<br />

1000<br />

100<br />

10<br />

Crosstalk Coupling on HC Degradation<br />

1<br />

0 0.1 0.2 0.3 0.4<br />

Ccoup/Ctotal<br />

◆ Lifetime drops 3 orders of magnitude as<br />

coupling increased from 0 to 35%<br />

◆ Most difficult/dangerous AC <strong>HCI</strong> phenomenon<br />

"For our high performance designs,<br />

<strong>HCI</strong> is an important issue. <strong>Celestry</strong>'s<br />

products make it easy for our designers<br />

to assess and prevent circuit-level<br />

reliability issues caused by <strong>HCI</strong> effects.<br />

-- STMicroelectronics<br />

<strong>NBTI</strong> Vg Dependency for Long Channel Device<br />

log DeltaVt/Vt (%)<br />

Delta Vt/Vt vs Time<br />

(W/L=10u/10u, T=125C, Vd=0)<br />

100.00%<br />

10.00%<br />

1.00% 1.00 10.00 100.00 1000.00<br />

log Time (min)<br />

Vg=1.45<br />

Vg=1.65<br />

Vg=1.85<br />

The engineering efforts of <strong>Celestry</strong> and<br />

TSMC have enhanced <strong>Celestry</strong>'s hot-carrier<br />

analysis software,"... "Offering designers a<br />

powerful tool for digital, mixed-signal and<br />

analog designs, particularly those using<br />

overdrive voltages. It also gives designers a<br />

higher level of assurance in the performance<br />

and reliability of their designs."<br />

-- TSMC<br />

HC Effects & <strong>NBTI</strong> in Circuit Operation<br />

Vit(t)<br />

Vout(t)


Step 2: Reliability Model Options<br />

Option 1: Aged Model<br />

The Aged model is simply an extension<br />

of the traditional SPICE model for <strong>HCI</strong>.<br />

Here is how it works: After calculating<br />

the "age" of each individual device in<br />

your circuit, Aged model parameters<br />

are automatically generated for the<br />

degraded devices.<br />

RelXpert also has options to limit the number of SPICE models generated to optimize<br />

simulation time with accuracy.<br />

Option 2: AgeMOS Model<br />

The AgeMOS model from <strong>Celestry</strong> is a new<br />

reliability analysis method for <strong>HCI</strong> and <strong>NBTI</strong><br />

circuit reliability simulation. AgeMOS is<br />

transparent to any MOS SPICE model and<br />

compatible with any simulator platform. The<br />

AgeMOS model is a significant improvement<br />

over other reliability models in the areas of<br />

model generation and accurate, efficient, and<br />

consistent circuit simulation. (Addtional<br />

AgeMOS model information, see section on<br />

"More on Built-in Reliability with the AgeMOS<br />

Model"<br />

Here is how it works: RelPro+ will allow you to take stress data, BSIMPro+ extracts the fresh<br />

and AgeMOS models for <strong>HCI</strong> and <strong>NBTI</strong>. RelXpert, the circuit level simulator, will allow you to<br />

analyze the circuit and view the results.<br />

More on Built-in Reliability with the AgeMOS Model<br />

<strong>Celestry</strong>'s AgeMOS model is a methodology for deep submicron CMOS reliability modeling<br />

and circuit simulation analysis. Using this methodology, IC manufacturers can provide a<br />

universal model to all of their IC design customers without SPICE model or simulator platform<br />

compatibility issues. The AgeMOS model for <strong>HCI</strong> and <strong>NBTI</strong> enables designers to do accurate<br />

and efficient reliability simulation analysis. This ensures optimal trade-off between yield and<br />

performance before product tape out. <strong>HCI</strong> and <strong>NBTI</strong> reliability analysis with the AgeMOS<br />

model prevents unnecessary reliability issues. <strong>Design</strong>ers can create designs and design<br />

shrinks that are more aggressive without overly pessimistic design guard bands and<br />

unnecessary silicon loss.<br />

RelXpert<br />

4


RelXpert<br />

5<br />

Step 3: Reliability Simulation<br />

Clear Results!<br />

RelXpert lists all measured<br />

transistors, their age degradation,<br />

maximum Igate and Isub, and many<br />

other device characteristics. You<br />

can use device degradation results<br />

to track which devices are more<br />

prone to <strong>HCI</strong> and <strong>NBTI</strong> degradation,<br />

and even quantify their individual<br />

immunity to <strong>HCI</strong> and <strong>NBTI</strong> effects.<br />

The resulting list of transistors will<br />

give you an accurate picture of<br />

transistor degradation, immediately<br />

enabling you to detect and identify<br />

the weakest spots.<br />

Gate Level HC and <strong>NBTI</strong> Reliability Simulation<br />

Fresh waveform vs. aged waveform with fresh<br />

SDF and aged SDF back annotation<br />

Here is how it works: RelPro+ will allow you to take stress data, using BSIMPro+ to get fresh<br />

and AgeMOS models for <strong>HCI</strong> and <strong>NBTI</strong>. RelXpert, the circuit level simulator, will allow you to<br />

analyze the circuit and view the results.<br />

Fres<br />

Aged<br />

<strong>HCI</strong> and <strong>NBTI</strong> continue to be important reliability issues that<br />

need to be properly addressed. The RelXpert tool makes it easy<br />

for designers to assess and prevent circuit level issues caused<br />

by these effects.<br />

The Ultimate <strong>Design</strong> at Your Fingertips!<br />

"Before and after degradation" waveforms give you accurate images of the circuit<br />

degradation. This will allow you to reevaluate the status of the design and give you the<br />

opportunity to redesign for faster, more reliable performance.


Customize the Simulation Set Up<br />

The Simulation Set Up Window gives you the opportunity to input values specific to your design.<br />

Specifying the Age Time allows you to accurately see the degradation of the chosen circuit at<br />

the selected circuit age.<br />

Lifetime Calculation lets you find out how long it will take your circuit to degrade to a certain<br />

degradation percentage. Just input the value and RelXpert will tell you the lifetime.<br />

The option to customize the simulation ensures that the result is accurate for the specified<br />

characteristics of your design.<br />

RelLink TM Interface to Cadence Analog <strong>Design</strong> Environment<br />

RelLink (for Cadence environments) displays<br />

individual device degradation results and backannotates<br />

the information directly onto your<br />

schematic.You can set RelXpert and RelLink to<br />

flag transistors that exceed a certain degradation<br />

threshold. Once detected, redesign the device or<br />

circuit and simulate again!<br />

To make the simulation process even easier and<br />

faster, use RelXpert API. RelXpert API is a set of<br />

library functions and utilities that allow you to call<br />

RelXpert simulations within the familiar GUI<br />

interface of your existing tools. Only RelXpert can<br />

deliver this complete solution to help you push the<br />

performance envelope without sacrificing reliability!<br />

<strong>HCI</strong> Effect on Circuit Waveforms<br />

Simulating circuit waveform degradation due to <strong>HCI</strong> is the key to more competitive designs.<br />

For example, you can display the effect that <strong>HCI</strong> degradation will have on your circuit delay<br />

and frequency waveforms.<br />

Overshoot and Undershoot Effects Revealed!<br />

Overshoot and undershoot can be the result of interconnect coupling or device capacitance<br />

feedback. RelXpert can capture such phenomena. This gives you the opportunity to redesign<br />

and ensure overshoot and undershoot are no longer threats to the performance or reliability<br />

of your design.<br />

Reliability Modeling Service from <strong>Celestry</strong> Labs<br />

<strong>Celestry</strong> Labs provides <strong>HCI</strong> and <strong>NBTI</strong> reliability model generation services. <strong>Celestry</strong> has many<br />

years of experience in reliability modeling, analysis, modeling service, and knowledge of deep<br />

submicron process reliability issues. Provide <strong>Celestry</strong> Labs with a fresh model and they will<br />

provide you with a reliability model in a timely fashion or <strong>Celestry</strong> Labs can provide fresh and<br />

aged models. Additionally; services may include consulting, <strong>HCI</strong>/<strong>NBTI</strong> process assessments,<br />

process variation monitoring, as well as training and technology transfer licensing.<br />

RelXpert<br />

6


<strong>Celestry</strong> <strong>Design</strong> <strong>Technologies</strong>, <strong>Inc</strong>.<br />

<strong>Celestry</strong> is the leading provider of physical design and analysis products<br />

that enable integrated circuit designers to achieve optimal performance from<br />

semiconductor process technologies. The Company offers software and<br />

services to electronic and semiconductor companies involved with the design<br />

of chips that are used in networking, communication, multimedia and<br />

computing products.<br />

Worldwide Headquarters<br />

<strong>Celestry</strong> <strong>Design</strong> <strong>Technologies</strong>, <strong>Inc</strong>.<br />

2560 Junction Avenue,<br />

San Jose, CA 95134-1902, U.S.A.<br />

Phone: (408) 451-1210<br />

Fax: (408) 451-1211<br />

Email: info@celestry.com<br />

http://www.celestry.com

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