Digital Systems Laboratory - Eskişehir Osmangazi Üniversitesi

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Figure 36: New Project Dialog 4 of 5The final dialog box in the new project process, shown in Figure 37, provides a summary of the projectthat Project Navigator will create based on your settings. Review the summary to make sure it matcheswhat is shown in Figure 37. If it does not, go “Back” and correct any errors. Otherwise, click “Finish” tocomplete this process.Figure 37: New Project Dialog 5 of 5At this point, the project has been created but it does not contain any source files. Create a new sourcefile for the two-input XOR. Either select Project New Source from the main menu or use the equivalentprocess in the Processes for Current Source window. The first of the New Source dialog boxes willappear, as shown in Figure 38.40
Figure 38: New Source Dialog 1 of 3Select Verilog Module to indicate you are creating a Verilog-HDL design module. Then, provide a filename as shown in Figure 38. You should not need to change the specified location, which should beinside the project directory you created earlier. Click “Next”.The next dialog optionally allows you to specify the ports of the module. This may also be done in the texteditor, when creating the module, so skip it at this stage. Simply confirm that the settings match thoseshown in Figure 39 and click “Next”.Figure 39: New Source Dialog 2 of 341
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Page 11 and 12: Part-2: Response of Logic Gates:Con
Page 15 and 16: XI. Using the same method get a Bin
Page 19 and 20: Fig. 17 Decimal digits represented
Page 23 and 24: Design this logic circuit with mini
Page 27 and 28: Table 12Inputs Outputs Connect data
Page 29 and 30: S R Q Q’1 01 10 11 10 0In the lab
Page 33 and 34: Table 15Procedure:1. Synchronous Se
Page 37 and 38: • The Library View tab displays a
Page 39: Figure 34: New Project Dialog 2 of
Page 43 and 44: At this point, you should end up wi
Page 45 and 46: does not, go “Back” and correct
Page 47 and 48: endmoduleAt this point, you should
Page 49 and 50: Figure 47: Modelsim Console WindowT
Page 51 and 52: The Restart dialog box appears, as
Page 53 and 54: Keep Hierarchy: NORTL Output: YesGl
Page 55 and 56: TIMING REPORTNOTE: THESE TIMING NUM
Page 57 and 58: Figure 53: New Source Dialog 1 of 3
Page 59 and 60: Figure 56: Entering Pin Location Co
Page 61 and 62: Figure 58: Generate Programming Fil
Page 63 and 64: • DC Power Jack, J4, at Left Cent
Page 65 and 66: Figure 64: Placing the PROM in Bypa
Page 67 and 68: Figure 67: Programming OptionsA pro
Page 69 and 70: In the dialog box of Figure 70, sel
Page 71 and 72: Figure 73: Programming OptionsA pro
Page 73 and 74: In the following HDL description, d
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Digital Systems Laboratory - Eskişehir Osmangazi Üniversitesi

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