Digital Systems Laboratory - Eskişehir Osmangazi Üniversitesi

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In the lab use two 7476 ICs to implement 4-bit asynchronous counter as shown in Figure 3. Connect Qoutputs of flip-flops to logic indicator lamps/LEDs of the CADET. Connect all clear (CLR) and preset(PRE) inputs to logic 1. Connect the CP input to the pulse output of the CADET and check the counter forproper operation.Write down the count sequence in Table 16. Identify this count sequence (up or down). Comment on whathappens after the application of 15 pulses to CP input.Table 16 Count sequence for the 4-bit ripple counter.34
Digital Systems Laboratory 2011Lab 10 : Logic Design Using Verilog HDL and Xilinx ISELaboratory Assignment #1ObjectivesThis lab is an introduction to logic design using Verilog-HDL with the Xilinx ISE 10.1i tools. No new logicdesign concepts are presented in this lab. The goals of this lab are for you to become familiar with theXilinx’s ISE Project Navigator tool for Verilog-HDL.Procedure:You will learn how to enter Verilog description of two inputs XOR gate and test your HDL definition inXilinx ISE. You should do everything described below. In the lab, you are not going to implement thedesign in a programmable logic device, therefore the lab ends after testing the circuit using ModelSim.Project Navigator OverviewThe Project Navigator is divided into four main sub-windows, as seen in Figure 32. On the top left is theSources in Project window which hierarchically displays the elements included in the project. Beneath theSources in Project window is the Processes for Current Source window which displays availableprocesses for the currently selected source. The third window at the bottom of the Project Navigator is theConsole window which displays status messages, errors, and warnings, and which is updated during allproject actions. The fourth window to the right is for viewing and editing text files. Each window may be1 resized, undocked from Project Navigator or moved to a new location within the main Project Navigatorwindow. The default layout can always be restored by selecting View Restore Default Layout.1 The experiments 10 is adopted from San Jose State University Department of Electrical Engineering, EE178 and isupdated with Xilinx ISE release 10.1i.35
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Digital Systems Laboratory - Eskişehir Osmangazi Üniversitesi

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