Digital Systems Laboratory - Eskişehir Osmangazi Üniversitesi

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Digital Systems Laboratory 2011Lab 8 : Flip-FlopsObjectives:• To become familiar with flip-flops.• To implement and observe the operation of different flip-flops.Apparatus7400 quad 2-input NAND gates (2)7476 dual JK master-slave flip-flops.LogicWorks or Proteus can be used in the digital circuit simulations.Procedure1. In the pre-lab using LogicWorks construct the circuit shown in Fig.25.Fig. 25You can use generic NAND gates or 74-00 and Binary Probes to simulate LEDs. Finally, we use SPDT forthe bouncing switch. Using the simulated circuit fill in the truth table.28
S R Q Q’1 01 10 11 10 0In the lab, build the RS latch shown in Fig.26. Use SPDT switch S as a bouncing switch. Q and Q’ outputsare connected to LED’s of the CADET. Verify the truth table of SR latch experimentally.Fig. 262. Modify the basic RS latch into a D latch by adding the steering gates and the inverter shown in Fig.27Connect the D input to the pulse generator of the CADET and set it at 1 Hz. Connect the enable input to ahigh through 1k resistor. Observe the output; obtain the truth table experimentally then change the enableto a low.Is the enable an active high or an active? Leave the enable low and place a momentary short to groundfirst on one output and then on the other. What happens?Fig. 273. The 7476 is a dual JK master-slave flip-flops with preset and clear inputs. The function table given inTable 13 defines the operation of the flip-flop. The positive transition of the CLOCK (CP) pulse changesthe master flip-flop, and the negative transition changes the slave flip-flop as well as the output of thecircuit.29
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Digital Systems Laboratory - Eskişehir Osmangazi Üniversitesi

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