Mid-term sem2-2012-2013-SOLUTION.pdf - MetaLab

With the solutionsMid-term Examination: Computer OrganizationSemester 2 2012-201321-November-2012Section A: State whether the following statements are TRUE or FALSE. Each question is 1mark. [10 marks]1. Computer Architecture is those attributes visible to the programmerAns: T2. The fundamental building block of the ENIAC machine was transistors.Ans: F3. The ENIAC was initially intended for making tables for estimating the trajectory ofmissiles in the World War.Ans: T4. The program counter stores the address of the next instruction to be executed.Ans: T T5. Instead of hard-wiring the units, the software is used to interpret and execute instructionsin a general purpose system.Ans: T6. Bus arbiter is responsible for allocating time on the bus.Ans: T7. The limiting factor in a computer’s performance has been internal memory access time.Ans: T8. If the memory has faster access time, then the cost per bit is less.Ans: F9. Mapping function determines how a block from the main memory is placed in the CentralProcessing Unit (CPU).Ans: F10. With a 24-bit memory address, the capacity of the main memory is estimated to be 16MB.Ans: T

Section B: Answer all questions. Each question is 10 marks. [30 marks]Question 1a) Given the following 8-bit binary value, compute its decimal equivalent. Show the works.[5marks]i. 10100001ii. 00011111i. 10100001 =161 , final answer 1, method = 1.5=2.5ii. 00011111 = 31 , final answer 1, method = 1.5=2.5b) Find the hexadecimal value for the given decimal, 244 10 . Show the works.[2 marks]244 10 = F4 16 = 1mMethod = 1m16 /244 = 16 X 15 =>240 [244-240]Balance 415=F and with balance , 4F4 16c) Write brief notes on the term “Transistors”.A transistor is a small size solid state device.It is made from silicon, less heat dissipation.[3 marks]Question 2a) Explain the instruction fetch and execute operations. Provide your answer with an appropriatediagram.Fetch operationProgram Counter (PC) holds address of next instruction to fetch[4 marks]

Processor fetches instruction from memory location pointed to by PCIncrement PCo Unless told otherwiseInstruction loaded into Instruction Register (IR)Processor interprets instruction and performs required actionsExecute operationProcessor-memoryo data transfer between CPU and main memoryProcessor I/Oo Data transfer between CPU and I/O moduleData processingo Some arithmetic or logical operation on dataControlo Alteration of sequence of operations• e.g. jumpCombination of aboveb) Interrupt is a mechanism that allows other modules to interrupt the normal sequence of processingin the CPU. Since there are many modules that might be sending an interrupt signal to the CPU,explain two methods of how the CPU might handle multiple interrupts.[6 marks]Disable Interrupt: In this method the CPU will entertain interrupt in a first come first servebasis, where when an interrupt handler is executed the CPU will not check on any otherinterrupt signal until the current interrupt handler has finished execution.Priority Interrupt: In this method each interrupt is set with a priority rank where interrupt with ahigher priority may interrupt an interrupt with a lower priority. If an interrupt handler is beingexecuted and an interrupt signal from a higher priority module comes in than the interrupthandler will be suspended and control is transferred to the handler of the coming interrupt.Question 3

a) Assuming a 4-way set associative cache (meaning 4 lines per set) with a cache size of 32KB, linesize of 64-bytes (word) and with a total of 512 lines. With main memory address bits of 22 bits, showhow the address would be formatted.[6 marks]Tag | set | wordWord = 64 bytes = 2 6 = 6 bit =2mSet = cache lines/no of lines per set = 512/4=128 = 2 7 = 7 bit =2mTag = 22 – (7 +6 ) = 9 bit =2mT=9 S=7 W=6b) ) Explain briefly how cache can help increase the performance of a computer.[4 marks]Cache is made-up of SRAM is which is faster technology for a memory.A cache may be a chip on its own or is designed inside the CPU chip itself.Even as a chip of its own the cache is attached to CPE by means of a local bus rather than onthe system bus.