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<strong>Defining</strong> <strong>SOC</strong> /<strong>SOPC</strong>System On a Chip,System On a Programmable Chip• « The electronics for a complete, working productcontained on a single chip ».Who said it mandates a processor ?The common perception is that all « intelligent »products are supposed to be based on a processorexecuting a program, hence a modified definition:• « A single chip including (at least) one processorand its peripherals »© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Different kinds of <strong>SOC</strong>/<strong>SOPC</strong>• ASICs.Huge NREs. Time-to-market is long, Risks are veryhigh. Probably only worth when the target volume isin millions of units.Typical markets : mobile phones, TVs & multimediaitems, automotive…• Structured ASICS.Intermediate solution, may address much smallervolumes (10k ranges) but do not offer all thebenefits from ASICs. Altera has Hardcopy.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Different kinds of <strong>SOC</strong>/<strong>SOPC</strong>• <strong>SOPC</strong> (FPGAs) with « hard » core(s).Does not seem to expand. Suffers some of theweaknesses of dedicated processors withoutoffering their advantages. The future will tell.• <strong>SOPC</strong> (FPGAs) with « soft » cores.This is the most popular category, on which we willnow focus.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
The “wrong” reasons…… to adopt <strong>SOPC</strong> :• ASICs have been embedding processor(s) for a longwhile. One important motivation, besides reducing thechip count, was to offer post-foundry flexibility.But this motivation is weak for an FPGA…• « Programming in C is easier than in HDL ».In many practical cases, this is simply not true.• « A somewhat similar application has beendevelopped once with a processor ».• « We have lots of software engineers available, buttoo few hardware engineers » !We can certainly find better reasons !© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
“All-hardware” solutionsIt is always possible to implement everything atRTL and completely avoid the processor.But …The design effort can become formidable in somecases (example : Ethernet Web Server !)The right idea is to combine and take advantage ofboth worlds while avoiding each’s downsides...© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Discrete processor weaknessesDiscrete processor-based solutions can offer advantages(+), but also suffer many weaknesses (-) :+ Cost, Power consumption, Integrated ADCs,All-in-one micro-controllers/DSPs- Obsolescence, (lack of) multi-source, low flexibility,performance issue, real-time events handling,S/W development tools may be hard to assess andqualify, different applications will likely require differentprocessors models and boards, bandwidth issue(Memory, I/Os), Firmware portability & longevity...© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Obsolescence (+rohs) ► Legacy µPsGoals• Minimize the software re-design efforts.• Re-use existing software « as-is ».Potential Solution• Legacy processors re-written as IPs in FPGAs.• Many available as Open Cores (GPL – LGPL)• Some offered in Commercial tools• Sometimes, « better » than the original (On-ChipDebug, or faster).Compatibilty (clock-cycles accuracy) is often priviledgedover better performance in this context.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Legacy µPs caveats• Many legacy peripherals may be required ascomplementary IPs. FPGA Design know-how isstrongly recommended.• Discrepancies vs original part tricky to track down.• For secured designs, non-regression may be difficultto prove.• Legal issues ?• Asynchronous issues (boards were essentialasynchronous) are difficult to handle in FPGAs.The popularity of this solution (though not overlyexciting technically), is expanding.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Demo IEmbedding a complete 8051-basedapplication inside a small FPGA :Is it a rocket scientist’s task ?We demonstrate now the use of Altium design software on aCyclone (Altera) board.This simple 8051-based design plays wav sound files sent by a PCover RS232.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Chip Count Reduction• … also helps reduce dependence on a given device.A µP-based design also involves peripherals, gluelogic, specific chipsets, interfaces etc... The completemulti-chips solution has few chances to offer multiplesources and miscellaneous compliances globally.In case of <strong>SOPC</strong>, there is only one device to qualify.• An <strong>SOPC</strong> is a more standard & versatile platform thatcan be re-used for many different designs.• <strong>SOPC</strong> offers better device independance, but may lockthe user with an FPGA vendor (which is often a moreacceptable constraint).© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Architectural decisions made safer• One µ-controllers (rich) family even offers a deviceselectionhelping software !• What if you change your mind and give up i2c forSPI ? Or need more PWM outputs ?• Want to address future applications with yet-to-bedefinedperipherals ?• In FPGAs, memory management is not tied to adedicated chipset.• Hardware implementations minimize theperformance bottleneck risks (next slide)© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
The beauty of ParallelismApplication Tasks can be split among hardware andsoftware, and moved across the boundary if required.• The ubiquitous 80% - 20% law often applies:20% of the code eats up to 80% of CPU ressources.This 20% is a good candidate for hardwareacceleration or hardware implementation.• How do you drive 80 PWM outputs with 4 µsresolution in real time with a processor ?<strong>SOPC</strong> does truly minimize the risks (at a cost)© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
<strong>SOPC</strong> excels when…• An Operating System is required.• Using high level protocols with ready-to-use S/Wimplementations (TCP/IP, Plug&Play, File Systems…)• GUIs with frequent changes (late marketingrequests…)• Re-using existing C code « as is » (cryptographygolden model, multimedia libraries, complex devicedrivers…).© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Hardware excels for…• Handling asynchronous events in real time.• Heavy processing (Digital Signal Processing)• Solving Bandwidth issues &Performance Bottlenecks• « Simple » operations repeated intensively (videoprocessing)• Moving and/or Processing large amounts of Datarapidly.• Demanding I/Os© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
The Altera solution - Nios II• Nios II is Altera’s 2nd generation Soft-Core 32 Bit RISC µP.• Developed internally by Altera, Harvard Architecture,Royalty-Free, all written in HDL including peripherals.Can be targeted to all Altera FPGAs.• Includes innovative features (Custom Instructions, TCMs,…)Nios IICPUDebugOn-ChipROMOn-ChipRAMCacheAvalon Switch FabricUARTGPIOTimerSPISDRAMControllerFPGA© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Nios II versions• Three Instruction Set compatible versions• Software code is binary compatible (no changerequired when CPU is changed)• FAST: Optimized for Speed• STANDARD: Balanced for Speed & Size• ECONOMY: Optimized for Size© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Nios II versionsNios II /fFastNios II /sStandardNios II /eEconomyPipeline6 Stage5 StageNoneH/W Multiplier &Barrel Shifter1 Cycle3 CycleEmulatedIn SoftwareBranch PredictionDynamicStaticNoneInstruction CacheConfigurableConfigurableNoneData CacheConfigurableNoneNoneTCM (Instr / Data)Up to: 4 / 4Up to: 4 / 00 / 0Logic Usage (LogicElements)1400 - 18001200 – 1400600 – 700CustomInstructionsUp to 256© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
<strong>SOPC</strong> BuilderOver 60Cores AvailableTodayAltera, Partner & UserCores− Processors− Memory Interfaces− Peripherals− Bridges− Hardware Accelerators− Import User Logic(ie. custom peripherals)Web-Based IP Deployment© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
<strong>SOPC</strong> Builder FlowProcessor Library<strong>SOPC</strong> Builder GUIConfigure ProcessorCustom InstructionsPeripheral LibraryHardware DevelopmentHDL Source FilesTestbenchSelect & ConfigurePeripherals, IPConnect BlocksGenerateIP ModulesSoftware DevelopmentNios II IDEC Header filesCustom LibraryPeripheral DriversSynthesis &FitterHardwareConfigurationFileVerification& DebugExecutableCodeCompiler,Linker, DebuggerUser DesignJTAG,Serial, orEthernetUser CodeOther IP BlocksQuartus IIAlteraPLDOn-ChipDebugSoftware TraceHard BreakpointsSignalTap ® IILibrariesRTOSGNU Tools© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Demo IIThe smallest Nios II system.(And it is still a 32-bits RISC processorprogrammed in C/C++ !)In this demo, we build from scratch, in real time, a systemincluding a Nios Processor and ports that we program inC++, on a Tornado (<strong>ALSE</strong>) Cyclone board. This board wasnot designed for <strong>SOPC</strong>, has no external memory etc…Conlusion : replacing a microcontroller by a <strong>SOPC</strong>/NiosFPGA solution is easy, cheap, and painless.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Avalon Switch FabricThe Avalon Switch Fabric is a significant contributorto the overall power and user-friendliness of the Altera<strong>SOPC</strong> solution :• Extremely flexible & versatile• Easy to create & hook custom peripherals• Transactions & principles are kept simple• Resources-friendly• Created and managed automatically by <strong>SOPC</strong> builder• Multiple Clock Domains & Crossings handled painlessly.• Etc…© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Fancy FeaturesOptions are available for “Power Users” :• DMA peripherals and controllers• Bus arbiters• Custom instructions• Tightly coupled memories• Multi-processors• Multi – Avalon architectures• Multi-processors solutions• Etc…© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Custom InstructionsMux User Logic into ALU path of Processor Pipeline toaugment Nios II Instruction Set & Accelerate the S/W.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
The processor is not all !Selecting the (right) processor is just the beginning,not the end ! You need also :• S/W development tools (C/C++ compiler, IDE,debugger, simulator, in-System debug, …)• A « System Builder » helping you tying all the partsboth as H/W and S/W elements. Altera has <strong>SOPC</strong>Builder and the Avalon Switch Fabric• Ready-to-use IPs for popular peripherals• JTAG UART with proper emulation & simulationmodel© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
And also…• Strong integration & automation with S/W(creating the SW goodies for a HW peripherals)• Support for Multiprocessors systems• Embedded Operating Systems ported on the <strong>SOPC</strong>platform.• Cross-platform Development tools• Utilities : Flash programming, Configurationmanager, flexible boot loader, CFI support…© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Demo III – Voice over IPThis system was designed initially to demonstratethe feasibility of <strong>SOPC</strong> for an industrial applicationthat required Voice of IP + industrial control andhandling of specific links.• Uses OOH323 Open H323 stack• Ported to Nios II Cyclone board with small efforts• Tested on IP phones• Small demo application built to :- call the IP phone and send a wave file- receive a call and record a wave file- exchange files with ftp© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Demo IIIVoice Over IP made easy :My FPGA board is a full-blown Linux computer !We demonstrate that an « old » Nios-Cyclone board is anadequate platform to run µClinux, transfer Linux applications(H323) over ethenet, and serve as a VOIP demonstrator.The FPGA board calls an Ethernet telephone and plays back theStarWars theme when the phone goes off hook.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
Conclusion• Legacy µPs Intellectual Properties may nicelyaddress obsolescence issues.• <strong>SOC</strong> on FPGAs (<strong>SOPC</strong>) is now a matureenough technology and tools like Altera’s arefacilitating its adoption for ambitiousembedded systems.© 2005-2006 Bertrand Cuzeau – <strong>ALSE</strong> – http://www.alse-fr.com
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