Design and Implementation of On-board Electrical Power ... - OUFTI-1
Design and Implementation of On-board Electrical Power ... - OUFTI-1 Design and Implementation of On-board Electrical Power ... - OUFTI-1
∆i L,1 + ∆i L,2 = 0, (5.16)V in D + (V in − V out )D ′ = 0, (5.17)V in = V out D ′ , (5.18)V out= 1 V in D ′ . (5.19)Since D ′ ≤ 1, this formula confirms the fact that a boost converter can only raise ormaintan equal the input voltage. This is actually reflected by the name of the converterwhich is related to the verb “to boost”.Introducing the losses, the expression becomesInductor designV outV in= η D ′ . (5.20)In steady state, the net change in the capacitor charge over one switching period must beequal to zero. During phase 1, the capacitor supplies the load. During phase 2, the currentfrom the inductor recharges the capacitor and supplies the load. The charge balance equationis thus−I out DT s + (I av − I out )D ′ T s = 0 (5.21)where I av is the average current in the inductor. This leads toI av = I outD ′ (5.22)The literature recommends to have a value of ∆i L which lie in the range of 0.2 to 0.4 I out(with maximum load) [16]. We write the constraint aswhere k ∈ [0.2; 0.4].Using the above equation, we get∆i L < kI av , (5.23)V in Df s L < k I outD ′ , (5.24)V in (1 − ηV inV out)< k I outV out,f s L ηV in(5.25)L > V in 2 out − ηV in )Vout 2 .outkf s(5.26)54
which provides the minimum value for the inductance.To find the largest possible value of the RHS of Eq. 5.26, we take the derivative of thenumerator N = Vin 2 V out − ηVin 3 , i.e. dN= 2V in V out − 3ηVdVin. 2(5.27)inThis givesV in = 2V out3η(5.28)This value of V in is used if it is in the range of possible V in for the converter. Otherwisethe closed V in within the range of possible V in is used.The peak current in the inductor is thus successively given byI max{ }= max I av + ∆i L2I max = max{IoutD ′}+ V inD2Lf s{ }I max = max IoutVoutηV in+ V in(V out−ηV in )2Lf sV out(5.29)(5.30)(5.31)The power losses in the inductor are equal to I 2 avR L , where R L is the series resistance ofthe inductor. They represent a loss of 1% efficiency ifR L < 0.01 V outD ′2I out= 0.01D ′2 R. (5.32)We now have all the elements necessary to design the inductor.follows:The procedure is as• The inductance is given by Eq. 5.26, where V in is given by Eq. 5.28 and at maximumI out .• The peak current in the inductor is given by Eq. 5.31, with maximum V in and maximumI out .• An acceptable inductor series resistance is given by Eq. 5.32.Capacitor designDuring phase 1, dv Cdt= i CC= −IoutC, and during phase 2, dv Cdt= i CC= Iav−IoutC.If the slope of v C during one phase is known, the voltage ripple on the capacitor ∆v C canbe obtained as follows:55
- Page 4 and 5: Contents1 Introduction 91.1 Cubesat
- Page 6 and 7: 4.4.2 Mean case . . . . . . . . . .
- Page 8 and 9: B Power budget worksheet 106C Pictu
- Page 10 and 11: design and the tests are delegated
- Page 12 and 13: Chapter 2Requirements of the EPS2.1
- Page 14 and 15: • The Single-Event Upset (SEU)Thi
- Page 16 and 17: the P-POD. RBF pins must fit within
- Page 18 and 19: Figure 2.6: Top view of the PC104 c
- Page 20 and 21: Chapter 3Design of EPS architecture
- Page 22 and 23: • Voltage (4) and current (5) at
- Page 24 and 25: Figure 3.6: The equivalent circuit
- Page 26 and 27: of our Lithium-Polymer batteries va
- Page 28 and 29: Figure 3.12: I-V curve of a solar p
- Page 30 and 31: 3.3.3 CapacityA important value to
- Page 32 and 33: Parameter SLPB723870H4 SLPB554374HN
- Page 34 and 35: of the batteries is kept between -2
- Page 36 and 37: Over Charge Prohibition 4.275 ± 0.
- Page 38 and 39: supplied in 5V. The circuit will be
- Page 40 and 41: Chapter 4The Power Budget4.1 Introd
- Page 42 and 43: Figure 4.1: P-V curve of a solar pa
- Page 44 and 45: 4.3.2 Efficiency of convertersTo at
- Page 46 and 47: Figure 4.3: Consumptions in % in me
- Page 48 and 49: Chapter 5Electrical Design of EPS5.
- Page 50 and 51: V outV in= D. (5.1)Since D ≤ 1, t
- Page 52 and 53: The power losses in the inductor ar
- Page 56 and 57: Using the value of ∆i L given by
- Page 58 and 59: There is no data about the case to
- Page 60 and 61: Capacitor selectionFour 10µF ceram
- Page 62 and 63: • Output voltage: 5V.• Maximum
- Page 64 and 65: Figure 5.12: Burst mode operation (
- Page 66 and 67: Figure 5.14: Simplified schematics
- Page 68 and 69: Figure 5.15: Worksheet for 3.3V con
- Page 70 and 71: sequently, the k was chosen above 0
- Page 72 and 73: where G 1 is the initial control-to
- Page 74 and 75: Figure 5.21: Measured Bode diagram
- Page 76 and 77: Figure 5.26: Equivalence between th
- Page 78 and 79: C f =12πf f R 0f,L f = R 2 0f C f
- Page 80 and 81: Figure 5.37: Schematics of the firs
- Page 82 and 83: R KR >1.45V100mA − 1.3A35= 23.07
- Page 84 and 85: The schematics is shown on figure 5
- Page 86 and 87: A commercial model meets all requir
- Page 88 and 89: Figure 5.45: Schematics of the heat
- Page 90 and 91: PrefixX7X5Y5Z5SuffixTemperature ran
- Page 92 and 93: 6.2.1 The second dissipation system
- Page 94 and 95: • The antenna deployment system.
- Page 96 and 97: 6.3.3 TestsThe engineering model of
- Page 98 and 99: 7.3 ActivitiesAs OUFTI-1 is designe
- Page 100 and 101: 8.1.2 DesignA model of Li-Po batter
- Page 102 and 103: [15] Fabien Jordan, Phase B Electri
∆i L,1 + ∆i L,2 = 0, (5.16)V in D + (V in − V out )D ′ = 0, (5.17)V in = V out D ′ , (5.18)V out= 1 V in D ′ . (5.19)Since D ′ ≤ 1, this formula confirms the fact that a boost converter can only raise ormaintan equal the input voltage. This is actually reflected by the name <strong>of</strong> the converterwhich is related to the verb “to boost”.Introducing the losses, the expression becomesInductor designV outV in= η D ′ . (5.20)In steady state, the net change in the capacitor charge over one switching period must beequal to zero. During phase 1, the capacitor supplies the load. During phase 2, the currentfrom the inductor recharges the capacitor <strong>and</strong> supplies the load. The charge balance equationis thus−I out DT s + (I av − I out )D ′ T s = 0 (5.21)where I av is the average current in the inductor. This leads toI av = I outD ′ (5.22)The literature recommends to have a value <strong>of</strong> ∆i L which lie in the range <strong>of</strong> 0.2 to 0.4 I out(with maximum load) [16]. We write the constraint aswhere k ∈ [0.2; 0.4].Using the above equation, we get∆i L < kI av , (5.23)V in Df s L < k I outD ′ , (5.24)V in (1 − ηV inV out)< k I outV out,f s L ηV in(5.25)L > V in 2 out − ηV in )Vout 2 .outkf s(5.26)54
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