Chip Scale Review - June 2008

June 2008• Semi-Annual Socket Issue• Wafer Thinning

CONTENTSJune 2008Volume 12, Number 4The International Magazine of Chip-Scale Electronics, Flip-Chip Technology,Optoelectronics Interconnection and Wafer-Level PackagingTHE COVERWelcome to our first socket issue of 2008, whichalso brings us to the halfway point in the year.Hoping to prosper, despite a soft economy, thetest and burn-in socket industry continues to gothrough its now-traditional cycles of consolidation.If you compare the exhaustive table we printedjust one year ago in June 2007 to the one wefeature in this issue, you’ll see some well-knownnames have disappeared. Not disappeared, really,have just been acquired by larger companies.A decade or so ago, almost anybody with a fewdollars had the cost of entry into socket making.Not so, anymore. The business—and thesockets—have become much more complex.Nick Langston, a true socket veteran with morethan three decades in the business, should know.He supplies our Socketology column in this issue.We’re also keying in on wafer thinning for thisissue. In case you didn’t realize it, thin is in!Consumer electronics have been a major driverfor electronics throughout the industry. Theconsumer’s demand for small and light isindirectly a major force behind the adoption ofwafer thinning and the growing use of 3D/stacked packages. Consumers want morefunctions in a smaller space at a very low cost.FEATURE ARTICLESI Can See Thinly Now! Is Wafer28Thinning the Final CSP Frontier?Terrence E. Thompson, Senior EditorThe industry demand for “smaller, faster, cheaper” is a dominant driver inthe growth of wafer-thinning technology. Multichip- and stacked packagesare now mainstream formats, thanks to the public’s growing appetite forultra-portable consumer gadgets. This article reviews the challenges foundin thinning wafers below 100μm, with 20μm emerging as the new reality.Test and Burn-In Sockets Are Scaling 34New Heights in Complexity and PitchRon Iscoff, EditorA decade ago, there were big socket companies and little socket companieswith generally ill-defined niches. If you wanted to socket a device, almostanybody could deliver a comparable device. Today, smaller companies don’thave much of a chance to capture market share, except by specializing.Technology has also made incredible leaps. Driven by smaller ICs, waferlevelprocessing and new package types, it takes dedicated research to keepup with customers’ demands.International Directory of Socket ManufacturersChip Scale Review Staff41CONTINUED >>We’ll see you in early July for our giantSEMICON West issue. Look for us then andaround Moscone Center.(Illustration for Chip Scale Review byDesign 2 Market) [design2marketinc.com]Chip Scale Review, at 7291 Coronado Dr., Suite 8, San Jose, CA 95129(ISSN 1526-1344), is published eight times a year, with issues inJanuary-February, March, April, May-June, July, August-September,October and November-December.Periodical postage paid at San Jose, Calif., and additional offices.POSTMASTER: Send address changes to Chip Scale Review magazine,7291 Coronado Dr., Suite 8, San Jose, CA 95129.Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 1

PUBLISHERS’ PAGEThe IWLPC—Still Setting thePackaging Conference PaceBy Terrence E. Thompson, Co-Publisher and Senior Editor[tethompson@aol.com]We are excited! Despite some technical conference pretenders that haveonly recently grasped the significance of wafer-level packaging (WLP)and 3D packaging, the 5th Annual International Wafer-Level PackagingConference, scheduled for October 13-16 will be the place to learn about the latestassembly/packaging and test concepts, processes, equipment and material sets.As you probably know, this annual conference we founded is co-presented by the SMTA[smta.org] and Chip Scale Review magazine. Together, we have organized an impressiveroster of workshops, conference presentations and panel discussions.If you attended last year’s keynote presentation by Oleg Khaykin, he made it exceptionallyclear that using WLP chips to implement package-on-package (POP) was Amkor’s future.The conference also covers many other popular single and multi-chip packaging conceptsincluding CSP, PiP, SiP and SoC.What should you expect this year? Look for two days of comprehensive workshopsfollowed by two days of paper presentations enhanced by panels on WLP and IC marketingchallenges. There will also be an exhibition by suppliers of services, equipment andmaterials.The keynote dinner speaker is Dr. Thomas H. Di Stefano of Centipede Systems, a longtimeinnovator and multiple patent holder in IC and chip-scale packaging. He will reflecton his observations on the wafer, IC and MEMS packaging opportunities to come.The conference will also have a special invited Wednesday morning speaker, Dr. StuartParkin of IBM’s Almaden Research Center. He will describe how he and his team developedthe breakthrough racetrack memory technology and its implications for future data storage.You won’t want to miss our Thursday panel. We’ve gathered experts on the semiconductorbusiness in China, India, Mexico and Vietnam for a special presentation called, “Wherein the World?” What are the drawbacks and benefits to locating and doing business inthese four countries? Find out on October 16.The IWLPC once again has participating speakers from the process-development orientedEMC3D Consortium [emc3d.org] and the end-user WLCSP Forum [wlscpforum.org].An international group of speakers will provide global perspectives. Youll see why we callthis an International conference.If your business involves using or producing chip-scale packages, wafer-level packagesor any other form of advanced semiconductor or MEMS packaging, you should attendthe IWLPC 2008 [www.iwlpc.org].Please plan on joining us at the Wyndham Hotel in San Jose. iSTAFFVOLUME 12, NUMBER 4The International Magazine of Chip-ScaleElectronics, Flip-Chip Technology, OptoelectronicInterconnection and Wafer-Level PackagingGene Selven Publisher Emeritus, Special Projects Director7291 Coronado Dr., Ste. 8, San Jose, CA 95129b 408.996.7016 > 408.996.7871gselven@aol.comKim Newman Co-Publisher/Sales Manager7291 Coronado Dr., Ste. 8, San Jose, CA 95129b 408.996.7016 > 408.996.7871csradv@aol.comTerrence Thompson Co-Publisher/Senior Editor2303 Randall Rd. #140, Carpentersville, IL 60110b 847.515.1255tethompson@aol.comRon Iscoff Editor & Associate Publisher929 Ebbetts Ave., Manteca, CA 95337b 209.824.1289 > 209.644.7747chipscale@gmail.comSteve Berry Contributing Editorb 408.369.7000 > 408.369.8021saberry@electronictrendpubs.comDr. Tom Di Stefano Contributing Editorb 408.321.8201 > 408.321.8701tom@centipedesystems.comDr. Subash Khadpe Contributing Editorskhadpe@semitech.comHarvey S. Miller Contributing Editor-at-Largeb 650.328.4550 > 650.327.2360h.miller@ieee.orgPaul M. Sakamoto Contributing Editor–Testb 925.924.9110 x148paul.sakamoto@inovys.comSandra Winkler Contributing Editorb 408.369.7000 > 408.369.8021slwinkler@electronictrendpubs.comThe Official Publication of the WLCSP ForumSUBSCRIPTION INQUIRIESJudy Levin Chip Scale Review7291 Coronado Dr., Ste. 8, San Jose, CA 95129b 408.996.7016 > 408.996.7871csrsubs@chipscalereview.comADVERTISING PRODUCTIONINQUIRIES AND REPRINTSKim Newman7291 Coronado Dr., Ste. 8, San Jose, CA 95129b 408.996.7016 > 408.996.7871csradv@aol.comADVISORSMark DiOrio MTBSolutionsDr. Tom Di Stefano Centipede SystemsCharles R. Harper Technology Seminars Inc.Nick Langston Ardent Concepts Inc.Dr. Guna Selvaduray San Jose State UniversityDr. Thorsten Teutsch Pac Tech USADr. David Tuckerman Tessera TechnologiesProfessor C.P. Wong Georgia Tech2Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]Copyright © 2008 by Gene Selven & Associates Inc.Chip Scale Review (ISSN 1526-1344) is a registered trademarkof Gene Selven & Associates Inc. Publishing headquarters arelocated at 7291 Coronado Drive, Suite 8, San Jose, CA 95129.All rights reserved.Chip Scale Review is published eight times a year.Subscriptions in the U.S. are available without charge toqualified individuals in the electronics industry. Subscriptionsoutside the U.S. (eight issues) by airmail are $60 per year toCanada or $60 to other countries. In the U.S., subscriptionsby first class mail are $40 per year.

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wet processingSolvent StripImmersion and SingleWafer ProcessingEtchUniform, Selective Etching onMultiple Process LevelsCoat/DevelopPhotolithography ClustersSolvent ImmersionBackside/Bevel CleaningSpin CoatingHigh Pressure SpraySpray EtchHot Plate Bake ProcessingHigh Pressure Needle DispenseUsing only milliliters of solvent per wafer,SSEC solvent processors combine batchimmersion and single wafer spraytechnology in one SEMI ® safetycompliant, dry-in/dry-out system. Highpressure sprays are entirely under closedloopcontrol for flow, temperature, anddispense arm motions.High Pressure Flow ControlStream Flow EtchWhether your requirements are for UnderBump Etching, with almost no undercut, orfor wafer thinning, SSEC’s patented singlewafer tools achieve more controlled resultsand substantial COO reduction, comparedto batch or alternative single wafer systems.SSEC’s exclusive WaferChek in-situadaptive process control ensures anoptimum etch on every wafer.Spray CoatApplication-specific coat and developclusters are configured for your exactprocess requirements, including thickresist processing. SSEC systems providestandard 95% uptime. The advancedmachine control technology enablessuperior uniformity within wafer, waferto wafer, and lot to lot, includingcomplete data tracking and operationwith programmable robotic sequencing.SSEC CompliancePressureTimeTi EtchAl EtchSEMI ® S2-0703aE SafetySEMI S8-0705 ErgonomicsFM 4910 MaterialsSECS GEM CCS 200 & 300CE MarkedETL ListedCu Etch3300Solid State Equipment CorporationPhone: 215-328-0700Email: info@ssecusa.comwww.ssecusa.com

ASSEMBLY LINESPondering Retirement and Other ThoughtsBy Ron Iscoff, Editor [chipscale@gmail.com]We are—God help us!—inone of those nasty timeswhere the industry andthe economy (assisted by the recordprice of petroleum and other necessarymaterials) have converged into a single,stinking mass of what we term a “flatmarket,” especially for equipment.Coming off a record 2006-2007, wewondered how our friends at the ICpackaging foundries would do withtheir Q1 reports.We had to put our April-May issue—the annual packaging foundry bible—tobed before any Q1 2008 financials arrivedfrom the providers. Now, they’ve arrivedand many people have reason to smile!Positive ReportsFor example, ASE [aseglobal.com], the#1 IC packaging and test provider disclosednet revenues of $811 million forthe first quarter of 2008, up 17% yearover-year,but down 15% sequentially.Chip assembly is a global business with the fourtop players in the billionnaire’s club.World Class Products andServices from the Expertsin Silicon Valley!Provider of quickturn BGA packageand SiP designs, prototypesand signal integrity solutionsWorld-class manufacturer ofhigh-productivity screen printingequipment for WLCSPOne-stop packaging foundryfor SiP devices, from productdevelopment through deliveryPTAPackaging FoundryPacific Gate Technologies is your Silicon Valley-based packaging consultantand technical sales representative for the electronics industry’sleading brands. We specialize in solving your SiP and WLCSP deviceproblems to meet the specialized demands of the RF and wireless market.3697 Millplain CourtSan Jose, CA 95121Tel: 408/705-4721 Cell: 408/393-3615danny.fields@pacgate-us.comwww.pacgate-us.com6Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

ASE’s net income for the quartertotaled $77 million (all figures havebeen rounded), up from $55 million in1Q07 and down from $122 million in4Q07. Diluted earnings per share for thequarter were $0.067 per ADS (AmericanDepository Share).Amkor Technology Inc. [amkor.com],the #2 shop, reported first quarter netsales of $699 million. Although this wasdown sequentially 6.3% from the fourthquarter of 2007 it was up 7.4% from thefirst quarter of 2007.Amkor’s first quarter net income was$72 million, down 23% from the fourthquarter of 2007 and up 108% from thefirst quarter of 2007. First quarter earningsper diluted share were $0.36, down22% from the fourth quarter of 2007,but up 100% from the first quarter of2007.Taiwan-headquartered SemiconductorPrecision Industries Ltd. [spilca.com],reported Q108 revenues of $490 million,keeping the company in third place.This was a 15.8 percent decline over theprior quarter, but 8.6 percent growthcompared to Q107.SPIL’s net income for Q108 plummeted,however, to $58 million, comparedto $157 million for the prior quarterand $126 million in Q107.Results Reflect Seasonal DemandAt #4 STATS ChipPAC [statschippac.com],the story was positive. Revenue for Q12008 was $427.2 million, an increase of9.4 percent over Q1 2007, although adecline of 10.4 percent from the priorquarter—no surprise there.Net income for Q1 2008, however,grew by 4.7 percent to $17.9 million or$0.08 per diluted ADS, compared to netincome of $17 million, or $0.08 perdiluted ADS in Q1 2007.Need I remind you, Esteemed Reader,that Q1 results are typically soft andreflect seasonal demand.New and Improved SiteShortly after last month’s column on websites went on press, I received an e-mailmissive from Lisa Lavin, STATS ChipPAC’sPR lady. Lisa asked me to look at theirnew and improved web site.I did, and as I told Ms. Lavin, I preferredthe former effort.What makes a good web site? A webdesign firm [grantasticdesigns.com],gives five items. While they seem quiteobvious, most web sites don’t followthem:Continued on page 48 >>More Performance... Aries ultra high frequency sockets have a mere 1 dBsignal loss at up to 40 GHz!!! Center probe and Microstrip sockets deliver morethan a half million insertions with no loss of electrical performance.More Choices... Aries offer a full range of sockets for handler-use, manual test andburn-in...for virtually every device type, including the highest density BGA and CSPpackages. Choice of molded or machined sockets for center probe and Kaptoninterposer models, too!Less Cost... in addition to extremely competitive initial cost, Aries replacementparts and repair costs beat the competition, assuring you of lowest total costof ownership.Less Wait... Aries can deliver the exact sockets you need within 6 weeks.So why settle? Aries makes it easy to get the world's besttest sockets. Call or visit our web site to find out how!ISO 9001CertifiedBristol, PA 19007-6810(215) 781-9956 fax: (215) 781-9845e-mail: info@arieselec.comwww.arieselec.comSensible Solutions... Fast!Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 7

Customize It.Test It.Validate It.When Efficiency & Reliability Are MandatoryGet the Advanced ® DifferenceStandard Ball Grid Array Socket Adapter Systems from Advanced Interconnections can becustomized to meet your special socketing requirements in test, validation and productionapplications. Advanced BGA Socket Adapter Systemsfeature patented solder ball terminals for process yieldscomparable with direct device attach. Multi-fingercontacts and screw-machined terminals assure reliableperformance, even in the most demanding applications.Plus, we’ll help you solve your toughest interconnectionproblems through our free application assistance program.0.50mm Pitch BGA Socketing SystemVisit www.advanced.com/bga to learn more aboutThe Advanced ® Difference in BGA Socket AdapterSystems & other interconnect solutions. www.advanced.com | 800.424.9850

TEST PATTERNSHow to Buy a Used Test SystemBy Paul M. Sakamoto, Contributing Editor–Test [paul_sakamoto@comcast.net]By the time you read this, we willhave been in the recession forhalf a year or more, dependingon who’s counting.Those of you who have the responsibilityfor buying test equipment, especially ATE,will have been getting beaten up by the bigbosses for cost reduction beyond the previouslyagreed-to budget and/or plan.‘Go Figure It Out!’Of course, they will not allow you toreduce the capacity of your test and sortareas due to reduced capital budgets. No,instead they will just tell you to “go figureit out,” or they will get someone who can!This is the typical scenario when wehave a semiconductor cycle that featuresflat-to-down revenues combined withhigher-than-ever volumes.For 50 years the song has remained thesame, and although I’ve only been in thegame for 30 of those years, some of the reallyold guys tell me I’m right on target here.One of the immediate responses tothis “no-win” corner is for the ATE buyerto go with used equipment. It seemsreasonable to many—if not most—managers in that position to do so.Furthermore, it can work out well, buthas some issues I will briefly outline:Used Equipment Positives:1. Very low acquisition cost (or at leastit better be).Continued on page 46 >>SuperButton and SuperSpring Contact ElementsHigh current, high frequency, low inductanceFlexible Design for All Your Engineering Needs • No NRE for Custom FootprintsSuperButton Connector TechnologySuperSpring Connector TechnologyBoard-to-Boardor Board-to-FlexCustom InterposersLand Grid ArrayPackage-to-BoardSocketsEngineering Programming & Test Sockets• Connector free—lengths down to 1.0mm• Array counts over 2,000• Pitches down to 0.5mm• Mating against BGA, LGA, QFN, CSP or flexsales@hcdcorp.com www.hcdcorp.com (408) 743-9700 x331Copyright © 2006 High Conection Density, Inc. All rights reserved. Information is subject to change without notice. “SuperSpring” and “SuperButton” are trademarks of High Connection Density, Inc.Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 9

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INDUSTRY NEWSIt’s Off to the Memory Races for IBMDr. Stuart Parkin, at right, is ready to conquer the racetrack memoryhorizons. (IBM photo)San Jose—In anewly releasedwhite paper,SEMI says thatproducers ofsemiconductorequipment andmaterials lose upto $4 billionannually tointellectualproperty theft.Lost revenuesfrom IP infringementrange fromone percent to2.5 percent oftotal annualindustry revenue, due to lost salesand market share.The SEMI report, Innovation atRisk: Intellectual Property Challengesand Opportunities, is based on a surveyof 49 SEMI member companies,representing 56 percent of the totalSan Jose—IBM says anew type of computermemory that combinesthe performance andreliability of flash andthe low cost and highcapacity of hard diskdrives is on the horizon.IBM Fellow Dr.Stuart Parkin andcolleagues at the IBMAlmaden ResearchCenter describe thefundamentals of atechnology called“racetrack” memory inthe April 11 issue ofScience magazine.Continued on page 16 >>SEMI Says Industry IP Theft May Be $2B-4B/YearWhether with a machine gun or by stealth, IP theft has become a majorcrime in the semiconductor industry, according to a new SEMI report.annual sales of the semiconductorequipment and materials business.Driven by Weak LawsThe study maintains that IP violationsare driven by weak IP protectionContinued on page 23 >>GSA Says Chip RevenueTotaled $267.5 Billion in 2007Intel’s CEO, Paul Ottolini, discussed the Internet at thelast Consumer Electronics Show in Las Vegas. (Intel)San Jose—The Global SemiconductorAlliance (formerly the Fabless SemiconductorAssociation), says semiconductorrevenue totaled $267.5 billion last year,with fabless and IDM revenues accountingfor 20 and 80 percent, respectively, of 2007chip sales. Continued on page 15 >>All-Star ForecastersSet for ConferenceSan Jose—An all-starpanel featuring a trioof the semiconductorindustry’s mostrespected forecasters isscheduled for October 15 at the fifthInternational Wafer-Level PackagingConference at the Wyndham Hotel.The panelists includeDr. Dan Tracy of SEMI,Jim Walker of Gartnerand Jan Vardeman ofTechSearch International.The 9 a.m.-10:30 a.m.panel is free to all conferenceregistrants andexhibitors, and includes Dr. Dan Tracyindividual presentationsas well as a question-and-answer period.Continued on page 12 >>SA N JOSE, CALIFO R NIAO C T O B E R 1 3-1 6, 2 0 0 8INSIDE NEWS• Reclaimed Si Wafer Market Growth Placed at27% by 2010 page 56Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 11

INDUSTRY NEWSIWLPC Continued from page 11 >>The experts will discuss, “GlobalTrends in IC Packaging and Materials.”Dr. Tracy is SEMI’s senior director ofindustry research and statistics. Prior tojoining SEMI, he was a research associateat Rose Associates, a prominent marketresearch and consulting firm specializingin electronic materials.He earned a bachelor’s degree inchemistry from the State University ofNew York, a master’s in materials scienceand engineering from the RochesterInstitute of Technology and a Ph.D. inmaterials engineering from RensselaerPolytechnic Institute.Record Revenues for MaterialsDr. Tracy says the semiconductor materialssector posted record revenues in2007 and is forecast to grow more than11 percent this year.Jim Walker is a research vice presidentfor Gartner and specializes in semiconductorassembly andpackaging analysis andforecasting. Prior to hisnine years at Gartner,he held executive postsat Hana USA, NationalSemiconductor andE.I. DuPont.Jim Walker He is a co-founderof the SMTA, as wellas a president emeritus and a formerSMTA board chairman. He holds abachelor’s degree in chemistry fromCalifornia State Polytechnic University.E. Jan Vardaman is president andfounder of TechSearch International,Austin, Texas, which has providedlicensing and consulting services insemiconductor packaging since 1987.She received a bachelor’s in economicsand business from Mercer Universityand a master’s in economics from theUniversity of Texas.She is also the editor of Surface MountTechnology: Recent Japanese Developments,co-author of How to Make IC Packages(published in Japanese by NikkanKogyo Shinbun) and the author ofnumerous publications on emergingtrends in semiconductor packaging andassembly. [iwlpc.org] ■Endicott Interconnect Receives$148.6M Contract ModificationEndicott, N.Y.—The U.S. Department ofDefense has awarded Endicott InterconnectTechnologies Inc.(EI) a $148.6M contractmodification for the continuation of thecurrent program to produce card frameassemblies including HyperBGA organicsemiconductor packaging, multichipmodule assemblies, printed circuit boards,functionally-tested circuit board assembliesand engineering services in support of ahigh reliability, high performance computingapplication. [eitny.com]multitest in your everyday life >>>Multitest contactorslast a lifetime.WorldwideEurope Asia USAwww.multitest.com • info@multitest.com12Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

Technologies, Inc.Your Global Provider of Leading EdgeSemiconductor PackagesNTK Technologiesoffers a wide rangeof cutting-edgeceramic and organicpackages forASICMPUSensorsMEMS• computer• consumer• telecom• medical• automotive• and hi relproductsMulti-LayerHigh FrequencyOPTORFHigh ReliabilityHigh DensityPhoenixArizonaIrvineCaliforniaSan JoseCaliforniaBostonMassachusettsAustinTexasDallasTexas602/470-9898949/580-0607408/727-5180508/820-0220512/340-0194972/235-1625Visit our web-site at www.ntktech.com

INDUSTRY NEWSGSA Continued from page 11 >>The findings were released in theGSA’s Global Semiconductor Fundingsand Financials Report. The quarterlyreport includes funding and financialdata for fabless, integrated device manufacturers(IDMs), pure-play foundry,intellectual property, electronic designautomation, design services and others.According to the GSA report, 206semiconductor companies (fabless, IDMand suppliers) raised $2.7 billion in 2007.In addition the top 20 semiconductorcompanies by 2007 revenue accountedfor $158.4 billion, or 58 percent of totalsemiconductor revenue. [gsaglobal.org] ■Taiwan’s Chip Makers Will Dominate the China MarketArlington, Va.—Liberalized Taiwaninvestment policies will lead to furthermigration of less profitable productioninto China and to an integrated GreaterChina semiconductor market increasinglydominated by Taiwanese companies.In its Q1 2008 Semiconductor Report,the U.S.-Taiwan Business Councilobserves that “although new investmentswill likely flow from Taiwan to China ata measured pace, it is important that thenew Taiwan investment rules for Chinaare released quickly.” This, says the Council,will enable companies to make informeddecisions and begin their operations.Continued on page 22 >>Top 15 Chip CompaniesNumber Company and Information1 Intel Corporation[NASDAQ: INTC]: $38,334,0002 Samsung[KSE: 5930]: $19,924,6153 Texas Instruments[NYSE: TXN]: $13,309,0004 Toshiba Corporation[TSE: 6502]: $12,977,3035 STMicroelectronics[NYSE:STM]: $10,001,0006 Hynix Semiconductor[KSE: 000660]: $9,188,4507 Renesas[Private]: $8,001,0008 NXP Semiconductors[Private]: $6,813,1649 Infineon Technologies AG[FSE: IFX]: $6,190,57410 Advanced Micro Devices[NYSE: AMD]: $6,013,00011 NEC Electronics Corporation[TSE:6723]: $5,862,18112 Freescale Semiconductor[Private]: $5,722,00013 Micron Technology[NYSE:MU]: $5,693,00014 QUALCOMM–QCT Division[NASDAQ: QCOM]: $5,619,00015 Fujitsu[TSE: 6702]: $4,760,338(Source: GSA)Check out our digital edition atwww.chipscalereview-digital.comChip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 15

INDUSTRY NEWSIBM Continued from page 11 >>Wire TrackWithin the next 10years, according to theIBM team, racetrackmemory (where thedata races around thewire “track”) may leadto solid-state productswith no moving parts,unlike disk drives.Racetrack technology,the researchers claim,could enable a handhelddevice such as an mp3player to store about500,000 songs or some3,500 movies—100x thecapacity of today’s mp3storage.In addition to offeringa much greater storagecapacity than is availabletoday, writes Dr.Parkin, the devices (IBM photo)would require much lesspower and generate far less heat. Theresult would be products with massiveamounts of storage that would run on asingle battery for weeks at a time and“last for decades.”Exciting Adventure“It has been an exciting adventure tohave been involved with research intometal spintronics since its inceptionalmost 20 years ago with our work onspin-valve structures,” said Dr. Parkin.“The combination of extraordinarilyinteresting physics and spintronicsmaterials engineering, one atomic layerat a time, continues to be highly challengingand very rewarding.”Racetrack memory, rather than storingdata as an ensemble of electronic charges,employs the “spin” of the electron tostore data. Since it has no moving parts,data can be rewritten endlessly withoutwear-and-tear.Dr. Stuart Parkin, lead author of the racetrack memory study, a newtechnology evolving from spintronics, will be the invited speaker at theInternational Wafer-Level Packaging Conference on October 15.In the review paper that describes thefundamentals of racetrack memory,“Magnetic Domain-Wall RacetrackMemory,” Dr. Parkin and his associatesdiscuss the use of magnetic domains tostore information in columns of magneticmaterial (the racetracks) arrangedin perpendicular fashion or horizontallyon the surface of a silicon wafer.Magnetic domain walls are thenformed within the columns dilineatingregions magnetized in opposite directionsalong a racetrack.Each domain has a “head” (positiveor north pole) and a “tail” (negative orsouth pole). The spacing between consecutivedomain walls (the bit length) iscontrolled by pinning sites fabricatedalong the racetrack.Ultimately, say the researchers, theracetrack will move into the third dimensionwith the construction of a novel 3Dracetrack memory device. [ibm.com] ■16Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

INDUSTRY NEWSPEOPLE IN THE NEWSColumnist Bird ReceivesJEDEC Award of ExcellenceArlington, Va.—James “Mark” Bird,a member of theexecutive staff ofNeoKinetics and aChip Scale Reviewcolumnist who specializesin standards,Mark Bird has received the2008 JEDEC Awardof Excellence, the association’s mostprestigious award. This Award is givenonly when a worthy candidate is identified,and was last presented in 2005.“The award recognizes those individualswho have held JEDEC leadershippositions as well as having made manysignificant contributions to the associationand the semiconductor industry,”according to JEDEC. [jedec.org]Rothstein Joins Plasma Etchas Eastern Sales ManagerCarson City, Nev.—Steve Rothstein hasjoined Plasma Etch,Carsen City, as easternregional U.S.sales manager.Rothstein is aveteran of the highSteve Rothstein vacuum depositionindustry, with over25 years experience in thin film coatings,plasma etching and vacuum technology.He has also been involved in U.S.start-ups Nordiko Ltd. and MantisDeposition Ltd.Rothstein is chartered with penetratingnew markets in the medical device,printed circuit, wafer processing, chippackaging and connector industries.[plasmaetch.com]Snyder Joins Hana Micron asPresident Americas/EuropeAsan, Korea—Industry veteranJack Snyder hasjoined Hana Micron,a Korea-basedprovider of ICassembly and test,in the new post ofJack Snyder president for theAmericas andEurope. In this post, Snyder will beresponsible for all manufacturing servicesbusiness outside the Korean market.Snyder’s previous service includespositions at Advanced SemiconductorEngineering, where he was VP–Americas;SPIL, where he served as a vice presidentand the United Technology and TestCenter, where he was president of theAmericas. [hanamicron.com]Schubring Joins Plastronics as Strategic Supply Chain ManagerIrving, Texas—Paul Schubring has joinedPlastronics Socket Co. as strategic supplychain manager, reporting to David Pfaff,Plastronics president.Most recently, Schubring served atIntel Corp. for 10 years in test andburn-in socket development.His role is to work with internationalsuppliers within the supply chain forsmooth deployment of new technology.Schubring earned a bachelor’s degree fromRensselaer Polytechnic Institute in mechanicalengineering and a master’s degree intheoretical and applied mechanics fromCornell University. [plastronicsusa.com]Staying Ahead in InnovativeBonding TechnologyWIRE BONDERS TEST EQUIPMENT LINE INTEGRATIONHeavy Ribbon Shows Our Leadership5th Generation – the only all-in-one bonderon the marketFine and heavy wire wedge, gold ribbon,gold ball – and now heavy ribbonLeading-edge heavy ribbon bonding technologywith minimal investmentwww.fkdelvotec.comF&K Delvotec Inc.27182 Burbank Avenue, Foothill Ranch, CA 92610phone (949) 595-2200, fax (949) 595-220718Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

What is a good partnership?Lewis & Clark Orville & Wilbur Wright Peanut Butter & JellyAt Johnstech, we consider our customer relationships to be partnerships andstrive to make sure that our Partner’s Testing goes as smoothy and efficientlyas possible. Our Test Contactors are known industry-wide for their outstandingelectrical and mechanical performance. But some might not know about our unmatchedService and Support. Whether it’s the Applications Engineer who analyzesyour Test requirements or the Scheduler who maneuvers to get you a 5-dayexpedited delivery, our entire expert staff is dedicated to providing you with thebest possible Test scenario. So those higher Yields and increased Profits you’llexperience? They are just some of the many value-added benefits you’ll seewhen you partner with Johnstech.High Performing Products. Superior Service. Exceptional Value.Johnstech is Your Partner-in-Test!Johnstech will be holding several, daily In-Booth Informational Presentations at SEMICON West 2008.To learn more and sign-up to attend, go to www.johnstech.com/SEMICONWest.

INDUSTRY NEWSEndicott Interconnect Inaugurates Advanced Microelectronics CenterEndicott Interconnect Technologies recently opened the Microelectronics Research Center.Endicott, N.Y.—Endicott InterconnectTechnologies recently inaugurated TheCenter for Advanced MicroelectronicsManufacturing (CAMM).The Center represents a collaborativeeffort by Binghamton University, CornellUniversity and EIT. Dr. Mark Poliks, R&Ddirector at EIT and technical director ofthe CAMM, hosted the event.EIT says the work conducted at theCenter will produce flexible, rugged,lightweight electronic components andinnovative products critical to nextgenerationapplications in areas thatinclude homeland security, lighting,energy and power generation, displaysand product identification and tracking.Plans for CAMM were initiated in2005 when the United States DisplayConsortium (USDC) selectedBinghamton University to manage thenew initiative.The USDC gave $12 million in equipmentto establish the CAMM, which ishosted by EIT with resources from Cornell.CAMM consists of a 10,000 squarefootarea and clean room. It includes anintegrated “roll-to-roll” (R2R) flexibleelectronics prototype manufacturing line,as well as an associated microfabricationlaboratory. Facilities also include a precisionlithography stepper, vacuum coatersand inline defect inspection.R2R, which integrates electronics onflexible plastic, in theory will result inthe more efficient production of electronicswith higher yields and lowercost. [eitny.com]Whatareyourcurrentburn-insocketsmissing?Cannis Named Technic’s Technical Services ManagerAnaheim, Calif.—Jeff Cannis hasjoined Technic, a supplier of platingchemistry and equipment, as manager,technical services. He earlier held keyroles in senior management at AmkorTechnology, Delphi Jade Technologiesand TRW Cinch Connector.Cannis, who holds a bachelor’s degreein chemistry, will also oversee the company’sanalystical lab, wafer-plating laband certain facilities management functions.[technic.com]Did You Know?Chip Scale Review is nowoffered in a digital format witha powerful search engine!Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 21

INDUSTRY NEWSTaiwan Continued from page 15 >>Taiwan President-elect Ma Ying-jeouhas declared that new investment guidelineswill focus on technology standards,export controls and intellectual propertyrights. Ma, a Harvard-educated lawyerand member of the KMT party, won thecountry’s presidential election onMarch 22.Technology TransfersUnder the new and liberalized guidelines,China will be opened wider forbusiness by Taiwan chipmakers. Ma haspledged to follow U.S. guidelines forsemiconductor technology transfers.In addition, the new administrationsays it will open direct air and shippingTHERE ARE NO SHORTCUTSTO A 5-MIL DOTMicro-volume dispensing requires three coretechnologies. Without them, you can forgetabout accurate volumes and placement:• DL Micro Valve with brushlessservo motor dispenses microvolumes of material in precise,repeatable patterns.• DL carbide auger and cartridgecombine for exceptional materialflow. Easily extracted forrapid cleaning.For dot sizes less than 10-mil, there is oneproduct line that is proven and trusted –by manufacturers in semiconductor packaging,electronics assembly, medical device, andelectro-mechanical assembly the world over.R• DL custom dispensing needlesprecision machined fromsolid stainless steel.Conically chamfered tipfacilitates material release.216 River StreetHaverhill, MA 01832 USAPhone: 978-374-6451Fax: 978-372-4889www.dltechnology.comMicro Valve is a trademark of DL Technology LLC. DL Technology is a registered trademark of DL Technology LLC.Vice president-elect Vincent Siew (left) andPresident-elect Ma Ying-jeou beat the drums at apre-election rally.links across the Taiwan Strait, withflights between Taipei and Shanghai tobegin as soon as July. Ma has alsovowed to lift investment caps on Taiwancorporate and individual investmentsin China.Since Ma’s KMT party controls threefourthsof the Taiwan legislature, Maand his new cabinet should be able toput his policies in place quickly, thereport observes.Council president Rupert Hammond-Chambers notes, “China’s chip industryis not developed enough to support amajor influx of cash and new fab buildingactivities, nor will it be ready withinthe next several years.“There is already too much excesscapacity in China, but Taiwan companiescan play the lead role in rationalizingand better integrating the market intothe global supply chain, as they buildtheir presence through direct investmentand mergers and acquisitions.”Silicon foundries, particularlyTaiwan’s two largest, TSMC and UMC,will be able to compete against China’sfoundries on their own turf, using asimilar level of technology.Singapore-headquartered SMIC, thethird largest foundry, has constructednew wafer fabs in China. Business, however,has not met capacity expectations.The move into China by the two largestfoundries will bring greater competitionto SMIC, the Council believes.[us-taiwan.org/tech] ■22Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

INDUSTRY NEWSIP Theft Continued from page 11 >>Regional IP ConcernsTaiwan 72%IncreasedSignalSpeedMainland China 71%Korea 66%North America 64%More PowerJapan 33%Europe 28%Serious to Very Serious0% 20%40% 60% 80%Percent of Respondents Expressing “Serious to Very Serious” Concerns about Each RegionLowInductanceTaiwan, followed by China, lead the way in IP violations. (SEMI)laws and weak enforcement and penaltiesin many regions of the world, as well asoutsourcing and off-shoring in Asia.Another factor, says the report, is theindustry’s unrelenting push for lowerprices in a consumer-driven market.About 90 percent of the companiesthat participated in the study reportedthey were vistims of some form of IPviolation including infringement, counterfeitingand theft of core technologies,core products, spare parts and components,trade secrets and trademarks.The major IP infringement violators,according to the report, are MainlandChina, Korea, Taiwan and NorthAmerica. In addition the study reports,about 53 percent of the companies whoresponded to the survey said the IP violationswere by their own customers,such as the chip producers.China, Taiwan Top InfringersAs shown in the figure, Taiwan andMainland China are nearly tied for IPviolations, with Korea and N. Americanext. Japan and Europe were the regionswith the fewest reported IP violations.The form and nature of IP violationsbetween violators in Asia and N. Americaare substantially different, the reportdiscloses. Because of stronger enforcementin N. America, companies generallyrefrain from intentional violations.Most activity in N. America is relatedto disputes about the validity of somepatents or certain claims, challengesagainst weak IP; or trade secret thefts—often by former employees; and unintentionalinfringement.Some 60 percent of the companiessurveyed took legal action against violators,but only 48 percent said they weresatisfied with the outcome.The report says in general, IP violationsby customers are driven by a desire toreduce costs, especially in the area ofspare parts and upgrades, sub-systemsand components.These violations include providingproduct details and parts specs andpricing information to third-party companiesto “entice them to provide(infringing) spare parts and assemblies.In addition, violations reportedinclude providing equipment and productaccess to competitors and givingprocess parameters and performancedata to competitors.The complete white paper may bedownloaded from the SEMI web sitesemi.org. ■StableResistanceHigherTemperaturesIncreasedStrokeReplaceablePinsChip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 23

solutionsfrom concept to sample analysis to realized potentialmicroelectronicengage analyze optimizeEngage early indevelopment withPanasonic. Collaboratewith our experts onconcept, prototypinganalysis andoptimization of yourdies, substrates,materials andmachines.Analyze your processand solve challengesupfront. OnlyPanasonic offerstrue-to-life conditionsthat remove andremedy many of thechallenges whenmoving a design toproduction.Rely on Panasonic’sexpertise inhardware, softwareand process torealize the fullpotential of yourproduct designs andincrease yourproductivity, qualityand profit.North America Europe AsiaPanasonic Factory Solutions Company of Americapanasonicfa.com 847-495-6100PFSAmarketing@us.panasonic.com

INDUSTRY NEWSJordan Valley Semiconductors Acquires U.K.’s BedeMigdal Ha’emek,Israel—JordanValley SemiconductorsLtd.,aprovider of semiconductormetrologyproducts, hasacquired Bede,aIsaac Mazor supplier of HRXRD(High ResolutionXRD) metrology for the semiconductorand compound materials industries.The U.K.’s Bede, with revenues of$11.6M in 2007, was in the country’s“administration phase,” the Britishequivalent of Chapter 11 bankruptcy.“The acquired technology will fitinto our product line almost seamlesslyLarson Rejoins AmkorTechnology as Executive VPChandler, Ariz.—Eric Larson hasrejoined AmkorTechnology Inc. asexecutive vice presidentfor the ProductManagement Group,reporting to KenEric Larson Joyce,COO.Larson will haveoverall management responsibility forAmkor’s product business units, includingwirebond products, wafer-level processingand flip-chip products, test services,R&D, emerging technologies andcorporate development.Larson began his career at HewlettPackard where he worked for 17 yearsin a number of senior managementpositions including general manager ofthe Integrated Circuits BusinessDivision and GM of the mobile businessoperation.He also served for seven years in seniormanagement positions at Amkorfrom 1996 to 2003, including presidentof Amkor’s wafer fab business and EVPof corporate development. [amkor.com]and will strengthen Jordan Valley’sposition as the market leader in x-raymetrology,” commented Isaac Mazor,Jordan Valley CEO.Bede X-Ray Metrology was foundedin 1978 as a spinout company fromEngland’s University of Durham. It hasbeen listed on the London stock exchange(LSE: BED) since 2000. [jvsemi.com]Lasky Joins STATSChipPAC as EVP/CSOSingapore—STATSChipPAC Ltd., asemiconductor testand packagingprovider, hasappointed Hal Laskyexecutive vice presidentand chief salesHal Lasky officer.Lasky will bebased in the U.S., reporting to L.K. Tan,STATS ChipPAC’s president and CEO,and will have overall responsibility forthe company’s worldwide sales andproduct line management organization.Prior to joining STATS ChipPAC,Lasky spent 24 years at IBM Corp.,where he held a number of key leadershippositions, most recently as vicepresident of worldwide semiconductorsales for IBM’s Global EngineeringSolutionsGroup.Lasky holds a bachelor’s degree inceramic engineering from RutgersUniversity and a Master’s degree inMaterials Science and Engineering fromColumbia University. [statschippac.com]Indium Appoints KobakRegional Sales ManagerClinton, N.Y.—Indium Corp. hasappointed Sherwin Kobak Pacificregion sales manager for BritishColumbia, Idaho, Northern California,Oregon and Washington, Kobak willbe based in Portland.[indium.com]TheSolutionH-Pin ®US Patent #7025602MaximizedPerformanceMadeAffordablewww.PlastronicsUSA.com800-582-5822Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 25

INDUSTRY NEWSCourt Dismisses Eleven FormFactor ComplaintsSeoul, Korea—FormFactor,a Livermoremaker of probe cards, says the SeoulSouthern District Court has ruled Koreanprobe card maker Phicom did not infringe11 claims of two FormFactor Korean patents.The patents in question are #252457and #324064, involving wafer-test products.The court decision was based on issuesNewMalaysia facilityto open inQ4/2007■ Quick-turn andmass-production■ Highly competitive,low-cost bumpingtechnology■ Exceptional qualitythrough high-levelexpertisePac Tech GmbHTel: +49 (0)3321/4495-100sales@pactech.dewww.pactech.dePac Tech USATel: 408-588-1925, ext. 202sales@pactech-usa.comwww.pactech-usa.comPac Tech Asia Sdn. Bhd.Tel: +60 (4) 6430 628sales@pactech-asia.comwww.pactech-asia.comTel: +81-3-5640-2282takahiro.okumura@nagase.co.jpwww.nagase.co.jprelated to the validity of the patentclaims and did not substantively addressFormFactor’s infringement allegations,the Livermore company said.“The Korean litigations are only one partof a comprehensive litigation strategy inmultiple jurisdictions involving multiplepatents, including our pending actionGlobal Low-CostWafer Bumping Services• Europe – USA – Asia •Available Processes■ Electroless Ni/Au under-bump metallization■ Ni/Au bump for ACF or NCP assembly■ Solder paste stencil printing■ Solder ball drop for wafer-level CSP■ Solder jet for micro-ball placement■ BGA and CSP reballing■ Wafer backside thinning and wafer dicingSpecial Features/Technologies■ Over 10 years experience■ U.S. Government Certified■ 4- to 12-inch wafer capability■ Wafer pad metallization: Al and Cu■ Solder alloys: eutectic SnPb37, lead-free,low-alpha, and AuSn■ Fluxless and contactless bumping for MEMSand optoelectronics■ Ni/Au interface for wire-bond applicationsThe leader in low-cost electroless wafer bumping.before the U.S. International TradeCommission.“Protecting our intellectual propertyrights against unauthorized use is importantas it helps enable our continuingcommitment to innovation,” said StuartMerkadeau, FormFactor’s general counsel.FormFactor’s other infringementclaims in Korea against Phicom, whichwere filed February 24, 2004 with theSeoul Southern District Court (PatentNos. 278342, 399210) and in August 8,2006 with the Seoul Central DistrictCourt (Patent No. 252457), are stillpending. [formfactor.com]Industry Vet Allen Joins i2aAs Op’ns-Production ManagerFremont, Calif.—Benjamin D. “Dave”Allen, a threedecadesveteran ofthe semiconductorindustry, has joinedi2a Technologies asproduction andBenjamin Allen operations manager.Allen most recentlywas production supervisor for VerticalCircuits in Scotts Valley, Calif.Earlier, he held quality managementposts at several leading semiconductorequipment companies, including GenmarkAutomation and Brooks-PRI Automation.Allen also served in key managementroles for quality, reliability, maintenance,training and customer service at severalchip makers, including AMD, MicroModuleSystems, National Semiconductor,Performance Semiconductor and QualitySemiconductor. [i2a-tech.com]Puttlitz, Totta Selectedfor 2008 IEEE AwardPiscataway, N.J.—Karl J. Puttlitz, Sr. andPaul A. Totta have been selected as therecipients of the 2008 IEEE Components,Packaging and Manufacturing TechnologyAward. [ieee.org]26Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

INDUSTRY NEWSSilicon Wafer Shipments Show Slight Decline in Q1San Jose—Worldwide silicon wafer areashipments remained essentially stable inthe first quarter of 2008, marginallydeclining 1 percent when compared tofourth quarter 2007 area shipments,according to SEMI’s Silicon ManufacturersGroup (SMG).In the SMG’s quarterly analysis of thesilicon wafer industry, the Group reportedthat total silicon wafer area shipmentswere 2,163 million square inchesin Q1 2008, compared to 2,185 millionsquare inches shipped during Q4 2007.Compared to Q1 2007, total area shipmentsincreased by three percent.The slight decline is “Consistent withthe conservative industry sentiment,”said Kazuyo Heinink, chairwoman ofSMG and vice president, new productmarketing, for MEMC ElectronicMaterials Inc.Despite the total decline, SMGreported 300mm wafer shipmentscontinued to grow. [semi.org]SMTA Announces Interactive EventsMinneapolis, Minn.—The SMTA will offertwo free interactive events at this year’sSMTAI: real-time chat rooms and theWii Interactive Lounge. The conferenceand exhibition will be held at Disney’sCoronado Springs Resort and ConventionCenter in Orlando, Fla., on August 17-21.[smta.org]A technician at Texas Instruments holds a 300mmwafer. (Texas Instruments)Dr. Marx Joins Alchimer asVP-Business DevelopmentMassy, France—Dr. Dan Marx hasjoined Alchimer S.A., a developer ofmaterials and processes used in themetallization of through-silicon vias, asvice president for business development.Dr. Marx was previously vice presidentof marketing for Burg Consulting andearlier director of new business developmentfor Praxair Electronics. He earneda Ph.D. in metallurgy from PennsylvaniaState University. [alchimer.com]Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 27

I Can See Thinly Now! Is WaferThinning the Final CSP Frontier?A major driver in the push for thinner wafers is the need to minimize signal interconnect distances and times.The industry demand for “smaller, faster, cheaper” are a dominant driver inthe growth of wafer-thinning technology. Multichip- and stacked packagesare now mainstream formats, thanks to the public’s growing appetite forultra-portable consumer gadgets. This article reviews the challenges foundin thinning wafers below 100μm, with 20μm emerging as the new reality.By Terrence Thompson,Senior Editor[tethompson@aol.com]Who needs fat wafers? No oneif you intend to build thin,light and energy-efficient products!One major driving force is thecompelling need to minimize signalinterconnect distances and times.28Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

This means using the shortest possibleelectrical paths. That, in turn, suggeststhe non-functional part of the wafer(or chip) is an impediment, since longerinterconnect paths often create problems.Convergence JuggernautToday, the best ways to achieve 3D ICwafer-level packaging integration involvethinning, through-silicon via (TSV)interconnects and wafer bonding.This convergence juggernaut of threewafer-based processes, including waferthinning, seems unstoppable.Obviously, the collective goal is to produceultra-thin, stacked 3D devices thatare electrically interconnected with theshortest paths using TSV technology.Dr. Dan Baldwin of Engent Inc.[engent.com] in Norcross, Ga., says,“With advances in wafer-thinning technology,3D packaging now provides arobust platform for achieving high levelsof integration, small package footprints,and thin package profiles.“For emerging applications, furthercomponent miniaturization with theadded benefit of 3D integration can berealized by face-to-face bonding of finepitch,flip-chip components and lowprofilepassives onto a redistributionlayer of another silicon component,such as a wafer-level chip-scale package.”Thinning InsightsEric Beyne, IMEC’s scientific directorfor interconnect technologies in Leuven,Belgium [imec.be], says, “At IMEC, forexample, we look into developing 3D-WLP stacks using WLP technologiessuch as redistribution, flip-chip bumpingand through-silicon vias.“In these stacks, we combine heterogeneousfunctions such as logic, memory,and analog sensors. IMEC is Europe’sleading independent research center inthe field of micro- and nanoelectronicsand nanotechnology. 1Beyne notes that 3D promises to offerAn IBM scientist holds a thinned wafer of silicon computer circuits, ready for bonding to another circuitwafer, where IBM’s advanced “through-silicon via” process will connect the wafers together by etchingthousands of holes through each layer and filling them with metal to create 3-D integrated stacked chips.(IBM Corp.)more than stacking 2D chips by connectingbond pads from one die to theother. Tighter 3D integration will benecessary to keep doubling the densityof designs every two years, consistentwith Moore’s Law. This requires splittingthe IC design itself into multiple, stackedphysical layers called 3D-stacked ICs(3D-SIC).TSVs and Thinning MicrocracksResearch and industry are already busytackling the technical aspects of 3D-SIC/IC says Beyne.One challenge is making vias sufficientlysmall with high aspect ratios.Another is handling wafers and chipsthinned well below 50μm, where chipsmay curl up, and display microcracksthat influence the transistors’ behavior.And when you finally have thoseultra-thin chips with micrometer-sizedvias, you have to find a way to positionthe vias of one chip precisely on thelanding pads of the second chip, whichis no trivial matter!The really difficult part of 3D-SIC/ICtechnology, however, will be the design,notes Beyne. The use of dense throughsiliconvias allows designs that solvesome of the interconnection problems of2D designs. At the same time, however,the complexity of 3D is many times thatof 2D, involving issues of testability,yield, quality, heat management, signalintegrity and choice of approach.Three-dimensional chip packagingwill become the dominant technologyin the industry, according to a studyfrom Frost & Sullivan in Palo Alto,Calif. [frost.com].A report, Global Trends in Electronic/Chip Packaging, maintains that 3Dpackaging technology will be “key” incatering to ever-increasing miniaturizationdemands in consumer electronics,game consoles and a wide variety ofhigh-speed memory devices.Currently, according to the report, theindustry focuses on interconnect technologies,signal integrity issues andmanufacturing capabilities. ResolvingChip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 29

all challenges involved in 3D systemdesign “remains very important to drivethis technology efficiently across thesupply chain.”“Advances in the field of packagingtechnologies are taking the packagecloser to the bottom-line wafer,” saysKrishnakumar Srinivasan, Frost &Sullivan’s Technical Insights researchanalyst.Thin Made EasyBonded, thinned wafers make compactnesspossible, but how are they thinned?Many thinning options exist dependingupon equipment vendor or packagingfoundry.Four common methods are used forwafer thinning: mechanical grinding,chemical mechanical polishing (CMP),wet etching/atmospheric downstreamplasma (ADP) and dry chemical etching(DCE).Due to its high thinning rate,mechanical grinding is the most commontechnique for wafer thinning.Grinding systems typically use a twostepprocess including a coarse grindingand a subsequent fine grinding.Subsequent processing is necessary toremove damaged layers created by thecoarse grinding step and to reduce surfaceroughness.Lapping, backlapping, thinning andpolishing of MEMS, silicon and compoundsemiconductor materials are usedin both prototype and production quantities.Wafers can be thinned to 100 micronsor less without edge deterioration.Dicing-before-grinding is one method that claims to improve yield on thin wafers. (DISCO Corp.)Thinning ABCsThere certainly are challenges when thinningwafers to less than 100μm. Reliabilityissues are being investigated, includingdie strength and subsurface damageassociated with these processes—as wellas the mechanical properties that includesurface roughness and wafer warping.The Die Products Consortium[dieproducts.org] has several specificationsfor thinned wafer die stacks thatinclude a maximum height of 1.2mm,which is heading for 0.8mm or lesssoon. This requirement includes the ballheight, substrate, wirebond loop heightand mold cap thickness, as well as thethickness of the die and interposers.ICs on fabricated wafers typically areabout 350μm thick. To be able to stackup to eight die in packages, the wafersare first thinned to 50μm or less.Commercially available grinding systemsuse a two-step process, including acoarse grinding (with thinning rates ofabout 5μm/sec) and a subsequent finegrinding (thinning rate=1μm/sec).Caution: Handle With Care!Handling thinned wafers is still a concern.At a 100μm thickness, a 200mmwafer can no longer support itself(150μm for 300mm wafers).Consequently, handling thinnedwafers and the die (after singulation)should be avoided unless absolutelynecessary. The result is that companiesare reluctant to do any testing or reliabilityscreening on the die itself aftersingulation, putting even more focus onthe known good die issue.One caveat to consider is that thephysical process of thinning eitherwafers or die inherently changes theirmechanical, electrical and/or opticalproperties.Thinning is possible for both entirewafers or individual die. A standardpatterned wafer can be thinned to athickness well below 75μm, dependingon size and inherent stresses. Individualdie can be processed even thinner.Thinned and polished wafers haveless backside stress than those subjectedto standard backgrinding. When diced,polished wafers have fewer backsidecracks and chip-outs.Thinning is also used to complete thedicing of a wafer sawn to a predetermineddepth. Thinning from the backsideleaves the surface as desired: rough,semi-polished or fully-polished. It is notuncommon to completely polish singulatedchips to a specified thickness andtolerance.Driving CompetitionThe integration of multiple chips in asingle package, specifically in 3D packaging,is creating tighter relationshipsbetween chip suppliers and end users.Stress relief in the production chain: After grinding, the wafer can be directly treated with the attachedback-grinding tape. (ASYNTIS GmbH)30Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

MicrobondDocfish –same behaviora billion timesMaterials for WaferBumping Applications01883 www.aim.deUmicore AG & Co. KGMicrobond - EPMHanau · Singaporewww.microbond.euUltrafinepitchSolder PastesWatersoluble andNo Clean Flux SeriesSoft Solder Spheresfrom Duksan Hi-MetalA perfect fit !

Don’t forget the essentials!If you’re planning to compete in the multi-billion dollarchip-scale packaging market, there are a few things you’llfind indispensable: marketing savvy, technicalknowledge and Chip Scale Review.We consistently present more original editorial onIC packaging than any competitor. And we do it from ourpublishing headquarters in Silicon Valley.If you plan to become a force in the international chip-scaleelectronics marketplace, make Chip Scale Review one of youressential sales tools.To learn how we can help you expand your sales goals,contact Kim Newman today at csradv@aol.com,or phone 408/996-7016.www.chipscalereview.com

sense to achieve the thinnest wafers andpackage stack—but carefully considerthe tradeoffs.Committing to 3D packaging offersfunctional integration in a minimumfootprint with low profile, low cost andquick time-to-market through theestablished packaging and chip-supplyinfrastructure.Assembly yields of 3D packaging withmulti-die stacks of thinned and bondedwafers are now approaching those ofpackages containing many chips.Packaging costs are often lower thanwith individually packaged chips, andpre-tested standard packages leave KGDyield as the only major determiner ofthe final cost of ownership.Polishing after grinding will remove most sub-surface damage.It’s also driving competition for theownership of the value-added featuresthat are intrinsic to this rapidly growingformat. 2Integration of chips with differentsilicon process technologies, includingCMOS, memory, SiGe and MEMS—impossible with SoC—as well as theintegration of designs and intellectualproperty in one package—may beachieved with established design tools,methodology and supply infrastructure.Higher reliability is gained by employingone package with fewer connections,as opposed to many packages with moreconnections to the final product board.Environmental compliance is assuredby the availability of these packages in“green” and Pb-free forms today. Thetypes of 3D packaging are often characterizedby how they are stacked, aschips, packages or passives.Early AttemptsIn 1997, a company in Sunnyvale, Calif.,introduced its atmospheric downstreamplasma (ADP) processing equipmentfor smaller, thinner, cheaper, and moreintegrated electronic devices.The ADP process is an ion-free chemicaletch that thins and removes damagewith a lower cost of ownership thanother backside etching and damageremoval methods. Any wafer, with orwithout bumps, and with or withoutgrinding damage, may be thinned usingthe ADP process to yield ultra-thinwafers that are flexible and resilient.A key benefit of plasma etching isthat is can provide better stress relief ofthinned wafers than conventionalremoval/polishing processes. 3Wafer BondingAs we noted in our April-May article onwafer bonding, if you intend to placestacked chips into the smallest spacepossible, take a close look at today’swafer-bonding tools and processes,because the technology may eliminatemany problematic Pb-free or wire bondinterconnects. 3 Bonding often makesConclusionsJust what does one need for 3D structuresand packages? Thinning equipmentvendors and many of the packagingfoundries offer insights and even designassistance on the most cost-effectiveapproaches.The choice of the 3D package type isdetermined not only by the needs of thefinal product, but also by the ownershipof the value-added that benefits thedevice supplier or OEM and the endusecustomer.For the thinnest wafers and chips,success is paced by the intertwineddevelopments of wafer thinning, waferbonding and TSV advancements. Ah,I can see thinly now! iReferences1. IMEC, Newsletter 52, April 2008, pg. 2.2. M. Karnezos, F. Carson and R. Pendse, STATSChipPAC, “3D Packaging Promises Performance,Reliability Gains with Small Footprints andLower Profiles,” Chip Scale Review, Jan.-Feb.2005, pp. 58-63.3. T. Thompson, “Wafer Bonding: From Niche toMainstream,” Chip Scale Review, April-May2008, pp. 50-53.Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 33

Test and Burn-In Sockets Are ScalingNew Heights in Complexity and PitchThe non-stop shrinkage in devices and packages has put socket designers to the test, giving them new mountains to climb to keep pace with theindustry they serve.A decade ago, there were big socket companies and little socketcompanies with generally ill-defined niches. If you wanted to socketa device, almost anybody could deliver a comparable device. Today,smaller companies don’t have much of a chance to capture marketshare, except by specializing. Technology has also made incredibleleaps. Driven by smaller ICs, wafer-level processing and new packagetypes, it takes dedicated research to keep up with customers’ demands.By Ron Iscoff, Editor[chipscale@gmail.com]Pick a socket, any socket. Holdit up to the light and slowlyturn it back and forth, to and fro.Examine it carefully, top to bottom.On the macro scale, one clamshellsocket looks pretty much like anotherclamshell socket, except it’s from adifferent maker.34Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

Amkor’s FusionQuad package and the proliferationof other new formats has thrown down the gauntletto socket designers.It’s where form meets function thatthe similarity between one maker’s testor burn-in socket typically diverges.To be sure, there are still a number ofme-too products in the socket realm andalways will be. You are going to findthese at the low end of the socket inventory.At the high end, socket makers arebusy trying to supply the now-burgeoningCSP and WLCSP markets.One issue that’s consistent in socketselection is contact pitch, the center-tocenterdistance between interconnects.This Aries Electronics high-speed, center probe test socket is formanual test of devices up to 13mm square.“Suppliers who don’t spend enough on R&D…will find themselves behind the 8 ball in the next fewyears,” says Plastronics David Pfaff.Shrinking PitchAnestel Corp. [anestel.com], Meridian,Idaho, recently had a customer requestfor a 700-lead, 0.2mm pitch BGA device.“Although I haven’t seenother requests for such ahigh pincount at thispitch,” says Darren Young,Anestel president, “thisisn’t the first request for an0.2mm pitch solution.“Since most semiconductormanufacturers arejust making the transitionto 0.4mm pitch, I was surprisedthat there is such agrowing demand for0.2mm pitch.”Young sees the demandcoming from the “WLCSPcrowd.”While WLCSPs haveeliminated the need for anATE socket, many of thechip makers still havesocket needs for bench test,engineering test, reliabilityand failure analysis, he observes. At thispoint, Young believes, the only viablesolution appears to be printed contactors—devicesthat are made via a photolithographicprocess.Printed contacts have also found theirway to applications where speed andsignal integrity are important. Chipmakers are looking beyond stampedpins or spring pins. While the use ofprinted contactors has typically been inengineering or characterization, Youngnow sees a growing demand for ATEand production test for printed units.This is one of RTI’s newest semi-custom socketproducts for engineering and production. It isdesigned to test optical packages that must betested “dead bug” in the handler.Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 35

The Antares Test 790 Series QFP burn-in socket isavailable in contact pitches of 0.4mm and 0.5mm.Price PressuresWith rising price pressures, chip makerswill be unable to afford the more costlyhigh-performance, spring-pin contactors,Young says. “The socket players whocome up with the low-cost, high-performancesolution are going to get all ofthe attention!”Socket suppliers are in almost universalagreement that the continuing miniaturizationof packages has a direct and dramaticeffect on the socketing industry.It continues to be a matter of “shrinkingpackages and pitches with increased I/Odensities,” says Afshin Nouri, presidentof Contech Solutions [contechsolutions.com], San Leandro, Calif.The result, adds Nouri, is that socketvendors must develop innovative waysto provide turnkey sockets for packageswith less than 0.4mm pitches. Thesesockets, in addition, have to be low cost,high-performance and offer accuratemechanical alignment for the package.The TrendsDavid Pfaff, president of PlastronicsSocket Co. [plastronicsusa.com], Irving,Texas, has observed three trends drivingthe socket market:First is the mechanical aspect—wheresub-0.5mm pitch devices have becomemore mainstream with larger pincounts(2000+). This drives both smaller contactelements at one end, says Pfaff, andbetter compliancy in contacts at the other.Next, he adds, is the electrical performance,where stable and lower resistance,lower inductance and better currentcarryabilities are needed for differentdevice types.Finally, says Pfaff, there is a growingevolution of the burn-in and testprocess, where companies are exploringthe overall test process more stringentlyat the wafer level to limit the need forfinal test and burn-in.The Next Socket ChallengesA few years ago, the next socket technologychallenges were reduced pitch,increasing I/O, higher power and thermalissues, according to Dr. James Forster ofAntares Advanced Test Technology[antares-att.com].Today, however, Dr. Forster asks youto remember the words of Englishwriter Aldous Huxley:“The charm of history and itsenigmatic lesson consists in thefact that from age-to-age nothingchanges and yet everything iscompletely different.”Ironwood Electronics’ LGA socket for 0.65mm pitch,the XG-LGA-7000, operates at a bandwidth up to40Gb with an insertion loss of less than 1 db.assembly to lower-cost locations suchas China,” Dr. Forster adds.Extreme ChallengesDesign and manufacturing engineers arefacing extreme challenges, Dr. Forstersays, to design, make and—perhapsmore difficult—assemble sockets withpitches of 0.3mm and below. “This willrequire the development of novel contactingtechnologies.”The increase in WLCSP packages isdriving the convergence of test and probetechnologies, but it can also presentissues of unique package size, he says.Since each chip maker appears to havedeveloped its own WLCSP format, the packagesize is easily handled in test sockets.The advantages of volume manufacturingfor burn-in sockets are eliminatedwhen these sizes move from a standard,such as 10 x 10mm—defined by themolded plastic—to a unique, geometrydie-driven format such as 9.63 x 9.42mm.Gerhard Gschwendtberger, businessunit manager–contactors, for Multitest,Rosenheim Germany, a company thatContech Solutions produces sockets for bothburn-in and test/test development.“Sockets with pitches that wereconsidered impossible a decade agoare readily available in productionquantities today. The drive for lowerprices requires a global presence assuppliers migrate manufacturing andMultitest’s ECON socket is available for QFN, QFPand SO packages down to 0.3mm.36Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

— A D V E R T I S E M E N T —PRODUCT SHOWCASEPEO – SemiconductorProcess FurnacesMulti-purpose, fastramping, bench-top,space saving andenergy efficientTemps up to 1150°CMultiple processg a s s e sUp to 300mm dia.wafers or equivalents u b s t r a t e sAlso availableSRO – SolderReflow OvensU.S. and CanadaR e p r e s e n t a t i v e :Please contact atv@pactech-usa.com or call408 - 588 - 1925www.atv-tech.deUnderfill for Your Currentand Future RequirementsMadison Magazine2006 Silver Medal WinnerNAMICS is a leading source for high technology underfills,encapsulants, coatings and specialty adhesives used by producersof semiconductor devices. Headquartered in Niigata, Japan withsubsidiaries in the USA, Europe, Singapore and China, NAMICSserves its worldwide customers with enabling products for leadingedge applications.For more information visit our websitewww.namics.co.jpor call 408-516-4611Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 37

Small but innovative socket vendors, such asCentipede Systems, can be successful by filling aniche. This is the company’s Centurion opticalsocket.makes test handlers as well as sockets,says there are a quartet of issues:• Package-driven requirements;• Leadfree coatings;• Increasing demand for Kelvin applications;and,• Test-cell interdependencies.The package-driven requirements, henotes, include smaller packages andsmaller pad/bump/ball structures. Thiscreates the need for greater accuracy atthe test socket and also demands moreaccurate package positioning, as definedby the test handler.At some point, he says, vision-controlledpackage positioning at the handler willbecome mandatory. “In the test socketarea, new materials like plastic with lessor no water absorption and suitableCTEs compared to IC packages, can helpovercome the positioning challenge.”Lens (Optional)Gimbaled BaffleClamshellCamera ChipLow Force ContactorA schematic of Centipede Systems optical socket.Package ProliferationAlthough pitch and electrical challengesare knotty problems, the growth of newpackage types has also meant moresleepless nights for socket providers.Jon Diller, international sales director,Synergetix [synergetix.com], Kansas City,Kan., observes that while productionsocket technology is advancing rapidly,chiefly dictated by package design, eachnew package family creates its own uniqueset of problems that must be solved.“For example,” says Diller, “withlarge-scale ASIC BGA devices, pincountand density are surpassing the mechanicalcapabilities of typical socket construction.“It is becoming common,” he adds,“to see requests for packages with pincountsabove 2000. This trend will driveissues with socket and load-board flexingand will also create serious challenges inboard routing.”Antares’ Dr. Forster also cites thedifficulty presented by new packages, inthis case Amkor’s FusionQuad.“The combination of QFN and QFPtypepackage in Amkor’s FusionQuad,with leads and contact pads, raises issuesof alignment and force applicationwhich require the integration of differentcontact technologies,” he observes.He says the initial flatness issues ofpackage-on-package formats have beenresolved with new latching mechanisms.However, Dr. Forster cautions, “If theneed to contact the pads on the top ofthe package, which has been solved inthe test socket world, moves into theburn-in socket world, further innovationwill be needed.”Pb-Free ConsiderationsNearly two years after the beginning ofthe Pb-free era in electronics, July 1, 2006,lead does not appear to be a major factorin the socket industry.Lead-free coatings, however, especiallypure tin variations, still create issues likematerial transfer and build-up, saysMultitest’s Gschwendtberger.Johnstech International’s Leaded ROL Series 200 and400 are offered in contact pitches down to 0.4mm.“From the contactor point of view,this situation can be improved by anoptimized combination of suitable contactspring coatings, contact force, contacttipgeometry and surface structures.Dedicated coatings can also make a significantdifference,” he says.The big challenge is to create a coatingthat maintains good electrical behaviorbut doesn’t allow the tin to accumulateon the surface. New surface structures(known as the Lotus Effect) can help toavoid material transfer effects, he reports.ConclusionThe difficult electrical and mechanicalrequirements will continue to driveinnovation in connector technology,from both an insulator (housing) andcontact technology perspective.“Suppliers with ‘me-too’ products orthose not spending enough in R&D willfind themselves behind the eight ball inthe next few years,” contends Plastronics’Pfaff.“In addition,” he adds, “the trend towardmore testing at the wafer level will shiftcapital spending away from packaged testand burn-in, and closer to the wafer fab.”While Dr. Forster’s quote fromHuxley is meant to illustrate that there’sreally nothing new under the sun—except everything—one thing reallynever does change and presents themost difficult challenge, he says, andthat’s cost, cost and cost! iChip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 39

SOCKETOLOGY WLCSPs Are Putting Sockets to the TestBy Nick Langston, Guest Contributing Editor [nlangston@ardentconcepts.com]Wafer-level CSPs (WLCSPs)are the ultimate chip-scalepackage. They are typicallyfabricated by encapsulating each die ofthe wafer with dielectrics and applyinga redistribution layer (RDL) of metalto fan out the pitch from the die pad tothe actual bump position.The wafers are bumped and diced,resulting in a CSP that is the size of thedie without the need for substrates, diebonding or other end-of-line processesspecific to standard leaded packagesThe intrinsic benefits of miniaturization,increased yield and lower costsmake WLCSPs an important technologyfor packaging service providers.As the technology is being increasinglyadopted, wafer-bumping costs arein decline and the WLCSP infrastructureis becoming well established. WithWLCSPs, final test isn’t being conductedin an expensive robotic handler, it isbeing accomplished with wafer probers.Market DriverThe demand for portable devices withembedded RF is driving the market forsmaller device packages.Micron SDRAM device with the RDL layer appliedRedistribution MetalFirst PolyimidePassivationFinal MetalMetal PlatingSecond PolyimideBallPolymers are dispensed on the wafer and act as the dielectric between the memory array and the metalused for re-routing from the pads. (Micron)The need to provide system-on-chip(SoC) devices with heterogeneousblocks of high-speed analog, digital andmixed signal plus RF within the sameform factor is requiring greater pincounts and smaller bump pitches.Leading edge SoCs with embeddedRF feature a pitch of 200 microns and abump size of about 120 microns with150-200 bumps on a 4.0mm die.The task of mechanically interfacing tothe device in production testing is not aserious problem for the wafer probers,but there are still some related issuesinvolved in testing these devices. Testingat-speed and burning-in the full wafersis still a rather expensive propositionand can generate an unscheduled delay.Technology GapWhen a test or product engineer requiresa high speed or RF characterization of asingle device, either from a customerreturn or system application, he willhave a difficult time finding a socketbecause of the existing “contacting”technology gap.Standard contacting techniques insockets face increasingly difficult times.Spring pins are a challenge at this verytight pitch. As the diameter of the pin isreduced to 120 microns or so, the lengthmust increase to generate enough forceto break the oxide on the bump. Then,as the length increases, the ability tooperate at high speeds is compromised.Continued on page 47 >>40Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

You can reach any advertiser’s home page by clicking on the URL.INTERNATIONAL DIRECTORY OF SOCKET MANUFACTURERSCompany NameAddressb Phone Year FoundedSockets Produced for:B=Burn-In,P=Production,T=Test/Test DevelopmentNewest Socket Family Specs(limited to advertisers)✔ Application (B, P, T)V Introduced Operating Temperature (Celsius)C Contact Pitch (mm)[web site]❉ Contact Additional Offices ✎ NotesNotes: Listings are taken directly from information provided by socketmanufacturers. For more information, contact the vendor’s web sites.Issue advertisers are listed in boldface type. CM=Consult Manufacturer.Advanced Interconnections Corp.5 Energy WayWest Warwick, RI 02893b 800.424.9850 1982P, T Compact HybridBGA Socket Adapter System✔ P, TV Oct. 2006 125°C 0.50 or 0.65[bgasockets.com]❉ Ron Bond, National Sales Managerrbond@advanced.com❉ Curt Wilmot, Product Application Engineercwilmot@advanced.comAEM Singapore Ltd.Singapore 555853b +65.64831811 1995P, T Elite Elastomer [aem.com.sg]❉ Sean Chuah, Sales & Application Managerseanchuah@aem.com.sg✎ Formerly AEM-EvertechAndon Electronics Corp.4 Court Dr.Lincoln, RI 02865b 401.333.0287 1988B, P, T Rollerball [andonelect.com]❉ Carol Remington, Customer Service Managerinfo@andonelect.comAnestel Corp.390 E. Corporate Dr.Meridian, ID 83642b 208.230.3343 2005B, P, T Connexus Pitch Transforming Products [anestel.com]❉ Kena Pegram, VP–Sales and Customer Servicekpegram@anestel.com✎ Formerly ConectL TestAntares Advanced Test Technologies2102 Quail Ave., Suite 2Phoenix, AZ 85027b 800.348.2505 2001B, T 790 Series Open Top QFN✔ BV April 2008 150°C 0.4 and 0.5[antares-att.com]❉ John Hartstein, VP–Sales & Marketingjohn.hartstein@antares-att.comAQL Manufacturing Services25599-D SW 95th Ave.Wilsonville, OR 97070b 503.682.3193 1986CM CM [aqlmfg.com]❉ Doug Kocher, Presidentdoug@aqlmfg.comArdent Concepts Inc.4 Merrill Industrial Dr.Hampton Beach, NH 03842b 609.926.2517 2003B, P, T ATE Socket for chip-scale RF devices✔ CMV Sept. 2006 -40° to 155°C Down to 0.4[ardentconcepts.com]❉ Steve Cleveland, VP–Business Developmentscleveland@ardentconcepts.com 930 Liberty Ct., Cupertino, CA 95014❉ Nick Langston, nlangston@ardentconcepts.comAries Electronics Inc.2609 Bartram Rd.Bristol, PA 08825b 215.781.9956 1972B, P, T High-Frequency Center Probe Sockets✔ TV Jan. 2008 -55° to 150°C CM[arieselec.com]❉ Frank Folmsbee, Sales Managerfrankf@arieselec.comCentipede Systems2110 Ringwood Ave.San Jose, CA 95131b 408.321.8201 2001B, T Centurion Metal Core Socket Family [centipedesystems.com]❉ Tom Di Stefano, Presidentinfo@centipedesystems.comContech Solutions631 Montague Ave.San Leandro, CA 94577b 510.357.7900 1995B, T Easy Fit Semi-Custom Sockets✔ B, TV Sept. 2007 -40° to 180°C 0.3 to 1.27[contechsolutions.com]❉ Kim Wagner, Marketing Managerkim@contechsolutions.com❉ Afshin Nouri, Presidentafshin@contechsolutions.comChip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 41

You can reach any advertiser’s home page by clicking on the URL.INTERNATIONAL DIRECTORY OF SOCKET MANUFACTURERSCompany NameAddressb Phone Year FoundedSockets Produced for:B=Burn-In,P=Production,T=Test/Test DevelopmentNewest Socket Family Specs(limited to advertisers)✔ Application (B, P, T)V Introduced Operating Temperature (Celsius)C Contact Pitch (mm)[web site]❉ Contact Additional Offices ✎ NotesNotes: Listings are taken directly from information provided by socketmanufacturers. For more information, contact the vendor’s web sites.Issue advertisers are listed in boldface type. CM=Consult Manufacturer.Custom Interconnects1505 W. Third Ave.Denver, CO 80223b 303.592.1903 1995P, T Ultra HF100 [custominterconnects.com]❉ Edward Petsuch, Vice Presidentepetsuch@custominterconnects.com✎ Formerly TecknitEmulation Technology(Interconnect Systems Inc.)759 Flynn Rd., Camarillo, CA 93012b 805.383.8480 1983B, P, T Hilo Flexible Interconnect System [emulation.com]❉ Perry Munroeperry@emulation.comEnplas-Tesco765 North Mary Ave.Sunnyvale, CA 94080b 408.749.8124 1994B, T Type S BGA [enplas-ets.com]❉ Jesse Reuter, WR Sales Managerjreuter@enplas-ets.comE-Tec InterconnectForel (Lavaux)Switzerland CH-1072b +41.21.781.08.10 1992B, P, T Open Top Clamshell✔ B, TV Jan. 2008 -55° to 150°C 0.40 to 1.27[e-tec.com]❉ Chris Haffter, President, chris@e-tec.com Mountain View, CA 94040❉ Bud Kundich, info-us@e-tec.comb 408.746.280042Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

You can reach any advertiser’s home page by clicking on the URL.INTERNATIONAL DIRECTORY OF SOCKET MANUFACTURERSCompany NameAddressb Phone Year FoundedSockets Produced for:B=Burn-In,P=Production,T=Test/Test DevelopmentNewest Socket Family Specs(limited to advertisers)✔ Application (B, P, T)V Introduced Operating Temperature (Celsius)C Contact Pitch (mm)[web site]❉ Contact Additional Offices ✎ NotesNotes: Listings are taken directly from information provided by socketmanufacturers. For more information, contact the vendor’s web sites.Issue advertisers are listed in boldface type. CM=Consult Manufacturer.Everett Charles TechnologiesSemiconductor Test Division4444 Centerville Rd., Saint Paul, MN 55127b 651.407.7777 1963P, T Gemini Kelvin [ectinfo.com]❉ Tony DeRosa, Product Managertony.derosa@ectinfo.comExatron2842 Aiello Dr.San Jose, CA 95111b 408.629.7600 1974P, T Duo Particle Interconnect Sockets [exatron.com]❉ Bob Garciabgarcia@exatron.comHigh Connection Density820-A Kifer Rd.Sunnyvale, CA 94086b 408.743.9700 1997B, P, T LGA Sockets Super-Button✔ High-frequency, high-current apsV CM -40° to 150°C Any array size or pitch to min 0.5[hcdcorp.com]❉ Charlie Stevenson, COO, charlie.stevenson@hcdcorp.com S. California: Packaging & Component SpecialistsSanta Ana, CA, sales@pcsrep.comb 714.834.1512High Performance Test48531 Warm Spring Blvd.Fremont, CA 94539b 510.445.1182 1995T CM [hptestusa.com]❉ Mark Malfatti, Sales Managermmalfatti@hptestusa.comChip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 43

You can reach any advertiser’s home page by clicking on the URL.INTERNATIONAL DIRECTORY OF SOCKET MANUFACTURERSCompany NameAddressb Phone Year FoundedSockets Produced for:B=Burn-In,P=Production,T=Test/Test DevelopmentNewest Socket Family Specs(limited to advertisers)✔ Application (B, P, T)V Introduced Operating Temperature (Celsius)C Contact Pitch (mm)[web site]❉ Contact Additional Offices ✎ NotesNotes: Listings are taken directly from information provided by socketmanufacturers. For more information, contact the vendor’s web sites.Issue advertisers are listed in boldface type. CM=Consult Manufacturer.InTEST Silicon Valley(InTEST Corp.)101 Nicholson Lane, San Jose, CA 95134b 408.678.9123 1981P V-Touch Extended Life Contactors [intest.com]❉ Jason Fong, V-Touch Product Managerj.fong@intest.comIronwood Electronics11351 Rupp Dr., Suite 400Burnsville, MN 55337b 959.229.8200 or 800.404.0204 1986B, T XG-BGA-XXXX, XG-LGA-XXXX✔ B, TV March 2008 -40° to 155°C 0.25 to 1.27[ironwoodelectronics.com]❉ Jason Cramer, Applications Directorjason@ironwoodelectronics.com❉ Ranjit Pail, R&D Directorranjit@ironwoodelectronics.comJohnstech International Corp.1210 New Brighton Blvd.Minneapolis, MN 55413b 612.378.2020 1990TLeaded ROL 400 Series✔ TV May 2007 -40° to 155°C 0.40 to 1.27[johnstech.com]❉ Jennifer Salhus, Marcomm Supervisorjssalus@johnstech.comLoranger International303 Brokaw Rd.Santa Clara, CA 95050b 408.727.4234 1983B, T CSP & QFN 0.35mm Pitch [loranger.com]❉ Debbi Stanley, Assistant to the Presidentdebbis@loranger.comM&M Specialties1145 W. Fairmont Dr.Tempe, AZ 85282b 800.892.8760 1976P, T CM [mmspec.com]❉ Sean Murraysdm@mmspec.comMicronics Japan Co.Tokyo, 180-8508, Japanb +81.422.21.0204 1970P, T J-Element [mjcelectronics.com]❉ Fred Megna, Technical Director, fredm@mjcelectronics.com MJC Electronics, Austin, TX 78758❉ Al Hutton, President, alh@mjcelectronics.comb 512.276.8951MultitestAeussere Oberaustr. 483026 Rosenheim, Germanyb +49.8031.406.0 1980TECON✔ TV July 2007 -60° to 200°C 0.3[multitest.com]❉ Gerhard Gschwendtberger, Business Unit Managerg.gschwendtberger@multitest.com Multitest Electronic Systems, San Jose, CA 95134❉ John Cunningham, Regional Manager, j.cunningham@multitest.comPhoenix Test Arrays3105 S. Potter Dr.Tempe, AZ 85282b 602.518.5799 1995T FIREBIRD C200 [phxtest.com]❉ Kat Smith, Operations Directorkat@phxtest.comPlastronics Socket Co.2601 Texas Dr.Irving, TX 75062b 800.582.5822 1969B, P, T H-Pin✔ B, P, TV July 2007 Up to 200°C Down to 0.5[plastronicsusa.com]❉ Steve Durrett, Sales Managersteve@locknest.comPrecision Contacts Inc.1008 Suncast LaneEl Dorado Hills, CA 95762b 916.939.4147 1981P, T Fine-Pitch Leaded Kelvin [precisioncontacts.com]❉ Ken Bottin, Saleskbottin@precisioncontacts.com44Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

You can reach any advertiser’s home page by clicking on the URL.INTERNATIONAL DIRECTORY OF SOCKET MANUFACTURERSCompany NameAddressb Phone Year FoundedSockets Produced for:B=Burn-In,P=Production,T=Test/Test DevelopmentNewest Socket Family Specs(limited to advertisers)✔ Application (B, P, T)V Introduced Operating Temperature (Celsius)C Contact Pitch (mm)[web site]❉ Contact Additional Offices ✎ NotesNotes: Listings are taken directly from information provided by socketmanufacturers. For more information, contact the vendor’s web sites.Issue advertisers are listed in boldface type. CM=Consult Manufacturer.Protos Electronics1040 Di Giulio Ave.Santa Clara, CA 95050b 408.492.9228 2003B, T High-Performance PTS Line [protoselectronics.com]❉ Adam Hopper, Sales Account Managera.hopper@protoselectronics.comRobson Technologies Inc.135 E. Main St.Morgan Hill, CA 95037b 408.779.8008 1989B, P, T Universal Multi-Site OpticalProduction Sockets✔ P, TV Jan. 2008 0° to 85° C 0.5[testfixtures.com]❉ David Dick, Applications Directordavidd@testfixtures.comRS Tech Inc.2222 W. Parkside Lane, Suite 117Phoenix, AZ 85027b 623.879.6690 1985B, P, T Flex Burn-In [rstechinc.com]❉ Richard Elliott, National Sales Managerrichardelliott@rstechinc.comSensata Technologies529 Pleasant St.Attleboro, MA 02703b 508.236.3800B0.4/0.5mm Pitch✔ BV 2006 125°C 0.4, 0.5[sensata.com]❉ Beverly Wilkins, Customer Servicebwilkins@sensata.com✎ Formerly Texas Instruments’ Interconnection BusinessSER Electronics(SER Corp.)3478 Buskirk Ave., Pleasant Hill, CA 94523b 925.746.7166 1998B, P, T RF-C Socket Family✔ CMV CM CMC CM[serusa.com]❉ Masamoto (Masa) Taira, Sales Managermtaira@serusa.comSynergetix Interconnect Devices5101 Richland Ave.Kansas City, KS 66106b 913.342.0404 1994TDyno QFN Test Socket✔ TV July 2008 -50° to 150°C 0.5[synergetix.com]❉ Jeff Tamasi, Sales Directorjeff@idinet.com❉ Kiley Beard, Sector Engineering Managerkileyb@idinet.com3M Electronic Solutions Division6801 River Place Blvd.Austin, TX 78726b 800.225.5373 1980Unitechno Inc.Tokyo 108-0023, Japanb +81.3.5476.5661 1988VN-Tek Inc.2262 Trade Zone Blvd.San Jose, CA 95131b 408.719.5000 2001Yamaichi Electronics USA475 Holger WaySan Jose, CA 95134b 408.715.9100 1956B, T OT BGA, Type 3 (963X Series) [3m.com/interconnects]❉ Michael Gieslermsgiesler@mmm.comB, P, T FC-008 0.2mm-Pitch Probe [unitechno.com]❉ info@unitechno.com USA: Cupertino, CA❉ Masa Fuchigami, Presidentb 408.255.3550P, T Custom Test Socket [vn-tek.com]❉ Jorge Santamaria, Accoount Managerjorgesm@vn-tek.comB, P, T NP506 QFN Open-Top [yeu.com]❉ Phil Turner, Marketing Coordinatorinfo@yeu.comYokowo Co. Ltd.(Circuit Testing Connector)Tokyo 114-8515, Japanb +81.3.3916.3111 1922P, T Hi-Giga Socket for Final Testand Wafer Level[yokowo.com] Yokowo America Corp., Sunnyvale, CA 94085❉ Alvy Padiyil, Sales Engineer, alvy@yokowo.comb 408.522.0326Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 45

TEST PATTERNSContinued from page 9 >>Since used ATE equipment is substantially more complex that a used car, youshould take at least the same care when buying it.2. Immediate delivery—presuming it isn’t currently on-line;3. Known reliability—or at least it can be if the seller has therecords. If the seller doesn’t have the records, look out!4. Buying a used piece of equipment, or threatening to, canreally lower the price of new equipment when you are negotiating.Used Equipment Pitfalls:1. Often, you get what you pay for.2. You can’t easily get manufacturer cooperation to refurbish,service or provide a warranty since it hurts the equipmentsales they badly need.3. Software licensing (See item 2 above!)4. Option configuration: It’s usually a lot easier to get a testerthan it is to get a tester configured the way you need it. If youdo need a new option, you may have an interesting negotiationwith the manufacturer, depending on how much leverage youhave in the way of new equipment purchases.5. Hidden, ongoing costs: In high-technology, used typicallyequates with old. Older ATE uses more space, power, slowercontrol computers, slower throughput, etc.Working Around the IssuesOf course, many of us have worked our way around theseissues before, but each turn of the chip cycle does bring newmanagers who haven’t done this dance. There are many detailsto be taken care of in your quest for inexpensive, used testContinued on next page >>46Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

SOCKETOLOGY This is a 0.5mm pitch socket designed for WLCSPs.Continued from page 40 >>At the 2007 BiTS Workshop, expertsnoted that to improve reliability andsurvivability in the “Drop Test,” the solderbumps on these devices is fashionedfrom SAC105, a notoriously abrasivemechanical interface to the testing pin.Buckling beams are an alternative butsuffer similar problems. Other contactschemes such as conductive elastomersand plated contacts are difficult to usebecause of the fragility of the WLCSPand the need to provide sufficient forcefor the elastomers to make contact.The die dimensional tolerance is ±20microns, so even the dimensional stabilityof the socket plastic is critical. I recommendyou shop early if you are going toneed test sockets for leading edge WLCSPs!ATE Load Board DesignA final consideration is the design of anATE load board to accommodate theWLCSP socket. A typical load board is4.0mm thick and would require a viaaspect ratio of 40:1!A possible solution, however, wouldbe a carefully designed fan-out interposeror microvias in the top layers ofthe ATE board.At these pitches, any vertical structuresmay cause radiation, crosstalk and ACI.Each of these effects will cause channel/signal impairment. It would be prudentto conduct a comprehensive signalintegrity analysis of the board and thesocket together. iMr. Langston is signal integrity managerfor Ardent Concepts and a 30-year veteranof the test socket industry.Did You Know? You can download,print, search or share any issue ofChip Scale Review in its digitial form![chipscalereview.com]TEST PATTERNSContinued from previous page >>capital equipment, but I suppose themain focus should be:1. Remember that you are likely toneed the help of the ATE manufacturerand you should leave somethingof value on the table for themif you ever expect to need theirhelp!2. Line up your programming andservice resources before you go tobuy and negotiate a deal. These arethe folks who can best help youevaluate the real value of anyprospective purchase.3. Carefully model the amount ofmoney you are saving versus theongoing expenses and throughputyou will likely be sacrificing. Forexample, your used unit may haveless throughput than a new one.So now, you will hopefully have sometalking points when your boss asksyou to look at used ATE. Best of luckin your efforts to beat the numbersand deliver those chips! iMr. Sakamoto has spent more thanthree decades in the trenches of the testindustry as an ATE user and seller. Hisexperience includes stints at Intel as atest engineer and Credence System,where he was vice president for memorytest systems. Most recently, he was CEOof Inovys Systems.[paul_sakamoto@comcast.net]CALENDARJULY15-17 SEMICON West,San Francisco [semi.org]AUGUST17-21 SMTA InternationalConference and Exhibition,Disney’s Coronado Springs Resortand Convention Center, Orlando, Fla.[smta.org]SEPTEMBER4 MEPTEC ENS Seminar—Semiconductor Roadmap Issues andSolutions: Closing The Gaps, DobsonRanch, Mesa, Ariz. [meptec.org]15-17 SEMICON Taiwan,Taipei, Taiwan [semi.org]25 3rd Annual Medical ElectronicsSymposium, Tempe, Ariz. [meptec.org]OCTOBER7-9 SEMICON Europa,Stuttgart, Germany [semi.org]Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 47

ASSEMBLY LINESContinued from page 7 >>• Easy to read; easy to navigate, consistentdesign, quick to download and easyto find.If every web designer and wanna-befollowed those five simple rules, the webwould be a kinder, gentler and moreattractive place!Pondering RetirementWhenever the industry goes soft, itseems like more people opt for retirement.We’ve noticed a definite uptick recently,starting with our own publisher, GeneSelven.Paul Sakamoto, our consulting editorfor test, has also opted to do his ownthing for the time being. This is Paul’sfirst break from the corporate world indecades, following the acquisition ofDr Subash Khadpe, the packaging industry’s historian, hasannounced his retirement. He posed recently against hisformer employer’s wall at the AT&T Works in Allentown, Pa.,site of the first transistor line.Inovys, the test company where hewas CEO.We recently received an e-mailfrom our friend Dr. SubashKhadpe, backend historian andempresario extraordinaire.After more than 30 years in thepackaging industry, Subash saysit’s time to pack it in. He was theeditor and publisher of the industry’sfirst newsletter devoted tosemiconductor packaging,Semiconductor Packaging Update.He was also the first to organizeand chair international conferencesin Silicon Valley on tape automatedbonding (TABCON) in 1989 and on flipchips (CHIPCON) and Flexible Circuits(FLEXCON) and packaging-related topicsin the 1990s.Subash has also been a stalwart contributorto this magazine for its entireexistence, and we wish him well!By the way, I don’t plan to retire anytimesoon; I have three voracious teenagersto feed and clothe and groom toleave home on their 18th birthdays! iHighest Performance with Proven Reliabilityin BGA, CSP and FBGA PackagesS.E.R. produces a wide range of IC test sockets, many which offer the advantage of being solderless. OurMini-Probe and double Mini-Probe IC sockets offer superior performance with the highest contact reliability.1.00mm FBGA Socket forActel, Altera, Lattice, Quicklogic andXilinx packagesMini-Probe PinsVarious types available foryour applicationswww.serusa.comS.E.R. ELECTRONICS U.S.A.3478 BUSKIRK AVENUE, SUITE 1020PLEASANT HILL, CA 94523PHONE: (925) 746-7166FAX: (925) 746-7153E-mail: mtaira@serusa.comS.E.R. CORPORATION1-14-8, KITA-SHINAGAWA, SHINAGAWA-KUTOKYO, 140-0001 JAPANPHONE: +(81)-3-5796-0330FAX: +(81)-3-5796-3210www.ser.co.jp E-mail: ser@ser.co.jpS.E.R. TAIWAN CORPORATION5F No. 9 LANE 126 HSUEH-F ROAD, SEC. 1TU-CHENG CITY, TAIPEI HSIEN, TAIWANPHONE: +886-2-2273-8792FAX: +886-2-2273-8790E-mail: tojanice@ms35.hinet.net48Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]

The event of the year for buyers,specifiers and producers of chip-scale andwafer-level packaging equipment, materialsand services will be presented in San Josefrom Oct. 13-16, 2008.RESERVE THOSE DATES FOR THE FIFTH ANNUALINTERNATIONAL WAFER-LEVEL PACKAGING CONFERENCEIf your business involves using or producingchip-scale packages, wafer-level packages or anyform of advanced semiconductor packaging, youshould attend the International Wafer-LevelPackaging Conference in October.Sign-up today to attend!THE GOLD STANDARD WORLDWIDE INSEMICONDUCTOR PACKAGING EVENTS!SCHEDULED EVENTSCo-presented byOct. 13-14Oct. 15Oct. 15-16Professional WorkshopsKeynote Dinner withDr. Thomas H. Di Stefano,Centipede SystemsTabletop Exhibits, TechnicalPresentations (two tracks),Special Panels and Poster SessionsIf your business involves developing, marketing orselling any equipment, materials or services usedby the people who use advanced semiconductorpackaging, you should be exhibiting at theInternational Wafer-Level Packaging Conference.Sign-up today to exhibit on Oct. 15-16!IWLPC TOPICSWLP Materials • 3D and Stacked DieManufacturing Processes • MEMSFlip-Chip Bumping • PhotoresistsPolymers for WLP • ElectroplatingCSP/MoP/PoP/PiP/SiP/SoPScreen Printing • Wire BondingThermal Management • UBM • TestingSA N JOSE, CALIFO R NIAVisit www.iwlpc.org or e-mailmelissa@smta.org for more information.O C T O B E R 1 3-1 6, 2 0 0 8Wafer-level packaging and much, much more!Platinum Sponsor Platinum Sponsor Gold Sponsor Gold Sponsor Gold Sponsor Gold Sponsor Book Sponsor Silver Sponsor Coffee Sponsors

Advantest Readies T5503Memory Test System IntroTokyo—Advantest Corp. has introduced theT5503 high-throughput memory test system.The company claims it offers the industry’shighest parallel test capability with up to 128devices.The T5503, slated for an August introduction,was developed specifically for the high-volumeproduction test of next-generation, high-speedDDR3-SDRAM.Advantest’s T5503 system is geared toward nextgenerationSDRAM.Next-generation DDR3-SDRAM featureslow power consumption through a reducedoperating voltage of 1.5V, compared to theDDR2-SDRAM’s 1.8V, as well as higher speedand higher volume data processing.Because of these generational advantages,manufacturers are transitioning to DDR3-SDRAM, and it is predicted to be in highdemand in a wide variety of fields, rangingfrom high-end desktop computers to notebookcomputers and digital consumer electronics.[advantest.com]Materials Heat TransferIs Focus of $6.8M GrantAnn Arbor, Mich.—A team led by KevinPipe, a University of Michigan mechanicalengineer and assistant professor, has receiveda five-year, $6.8-million grant from the AirForce to examine the problem of heat transferbetween materials—a barrier to more power-Oerlikon Esec Launches 2100 xP Die BonderCham, Switzerland—OerlikonEsec has launched a new300mm die bonder generationwith the introduction of its2100 xP die bonder family,which targets the high-volumeepoxy die attach market.Three key developments areincorporated into the newmachine. First is the company’sPhi-Y pick-and-place, whichcombines pivoting and linearmovements. Designed for higheststiffness and speed, thepick-and-place achieves anaverage dry cycle time of only167ms. The bonder also offersa claimed placement accuracyof 20μm (3 sigma) under highvolumeprocess conditions.Next, the bonder incorporates severalcapabilities to keep downtime low, includinga new strip handler that automaticallyadjusts its four independent clamps accordingto the new substrate demands.Plasma Etch Inc. Debuts Low-Cost Plasma EtcherThe PE-100 is geared to universities and small R&Dlaboratories.Oerlikon Esec’s new 2100 xP die bonder is the first of the company’snext-generation machines.The company is also introducing what isterms a “new and highly advanced humanmachineinterface, which is the most userfriendlygraphical user interface availabletoday.” [oerlikon.com/esec/]Carson City, Nevada—Plasma Etch Inc.has introduced a new, low-cost plasma etchingsystem, the PE-100, for universities, small R&Dlaboratories and pilot production facilities.The PE-100 provides a modestly sizedvacuum chamber that accommodates up to240" of process area capacity per run cycle.An RF power supply with matching network,vacuum pumping, and PLC-based processvacuumcontroller with touch-screen programmingis all included as a “turnkey” package.Any process developed on the PE-100 canbe scaled up to larger Plasma Etch systems.All Plasma Etch systems operate using adry RF-induced ionized plasma process, whichenables the uniform removal of undesirablecontaminants and provides a hydrophilic surfacefor adhesion of subsequent part processing.[plasmaetch.com]Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com] 51

INDUSTRY NEWSReclaimed Si Wafer Market Growth Placed at 27% by 2010San Jose—Theworldwide reclaimwafer market isestimated at $679million in 2007and forecast toreach $859 millionin 2010.Growth is drivenby 300mm wafers,which maintainshigher average sellingprices on asquare-inch basis.However, due tothe proliferation ofsuppliers, intense price pressure willcontinue, specifically on 300mm,according to Lara Chamness, seniormarket analyst for SEMI.Pricing of 200mm and smaller wafersis expected to remain relatively stable,adds Chamness, due to the tight siliconsupply and high utilization rates ofthese lines.41%21%12%12%6%5%3%JapanTaiwanN. AmericaEuropeROWS. KoreaChinaThe 2007 reclaimed wafer market revenue by region (SEMI)The Japan region is the largestreclaim market in both revenue andnumber of wafers, and it is expected toremain so for the duration of the SEMIforecast because of the prominent positionof the reclaim companies there.Taiwan is the second largest marketregion for reclaimed wafers, followed byNorth America. [semi.org]ADVERTISING SALESN. California and Northwest, ReprintsKim Newman Chip Scale Review7291 Coronado Dr., Ste. 8, San Jose, CA 95129b 408.996.7016 > 408.996.7871csradv@aol.comS. California, Arizona, Colorado, Florida and TexasRon Levinson7212 E. Whistling Wind Way, Scottsdale, AZ 85255b 480.473.4800 > 480.473.7008ron@levinsonmedia.comEast CoastRon FriedmanP.O. Box 370183, Hartford, CT 06137b 860.523.1105 > 860.232.8337chipscalereview@comcast.netMidwestJohn Byrne Facinelli Media Sales1400 E. Touhy Ave., Ste. 260, Des Plaines, IL 60018b 847.699.6049 > 847.699.8681jabber10@ix.netcom.comAustria-Germany-SwitzerlandRalf Gerbracht IMP Intermedia Partners GmbHIn der Fleute 46, 42389 Wuppertal, Germanyb +49.202.27169.17 > +49.202.27169.20gerbracht@intermediapartners.deKoreaKeon Chang Young Media407 Jinyang Sangga, 120-3 Chungmuro 4 gaChung-ku, Seoul, Korea 100-863b +82.2.2273.4819 > +82.2.2273.4866ymedia@chol.comInternational SalesJudy Levin Chip Scale Review7291 Coronado Dr., Ste. 8, San Jose, CA 95129b 408.996.7016 > 408.996.7871csrsubs@aol.comADVERTISER INDEXFor more information about any of these advertisers and their products, visit www.chipscalereview.comor click on their link in the digital edition at www.chipscalereview.com-digital.com.Aceris aceris-3d.ca . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Advanced Interconnections advanced.com/bga . . . . . . . . . . . . . 8, 37Antares Advanced Test Technologies antares-att.com/zsocket . . . . . . 1Aries Electronics arieselec.com . . . . . . . . . . . . . . . . . . . . . . . . . . 7Ardent Concepts Inc. ardentconcepts.com . . . . . . . . . . . . . . . . . . . 6Artwork Conversion artwork.com . . . . . . . . . . . . . . . . . . . . . . . . 37ATV atv-tech.de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Chip Scale Review chipscalereview.com . . . . . . . . . . . . . . . . . . . 32Contech Solutions contechsolutions.com . . . . . . . . . . . . . . . . . . . 46DL Technology dltechnology.com . . . . . . . . . . . . . . . . . . . . . . . . 22Dynamic Test Solutions dynamictest.com . . . . . . . . . . . . . . . . . . . 27E-tec Interconnect Ltd. e-tec.com . . . . . . . . . . . . . . . . . . . . . . . . 37F&K Delvotec fkdelvotec.com . . . . . . . . . . . . . . . . . . . . . . . . . . . 18HCD Corp. hcdcorp.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9HDI Solutions hdi-s.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Indium Corp. of America indium.com . . . . . . . . . . . . . . . Back CoverIronwood Electronics ironwoodelectronics.com . . . . . . . . . . . . . . . 16IWLPC iwlpc.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49KYEC kyec.com.tw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Johnstech International johnstech.com/semiconwest . . . . . . . . . . . 19Malico malico.com.tw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Micro Control Co. microcontrol.com . . . . . . . . . . . . . . . . . . . . . . 43Multitest multitest.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Namics namics.co.jp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37NTK Technologies ntktech.com . . . . . . . . . . . . . . . . . . . . . . . . . . 13Pacific Gate Technologies pacgate-us.com . . . . . . . . . . . . . . . . . . 6Pac Tech pactech-usa.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Panasonic Factory Automation panasonicfa.com . . . . . . . . . . . . . . 24Plastronics Socket Co. plastronicsusa.com . . . . . . . . . . . . 21, 23, 25Robson Technologies Inc. testfixtures.com . . . . . . . . . . . . . . . . . . 3Rudolph Technologies rudolphtech.com . . . . . . . . . . . . . . . . . . . . 17SEMI semi.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50SER USA serusa.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48SMTA smta.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Sensata sensata.com . . . . . . . . . . . . . . . . . . . . . Inside Front CoverSpeedline Technologies speedlinetech.com . . . . . . . . . . . . . . . . . 10SSEC ssecusa.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 5Synergetix (IDI) synergetix.com . . . . . . . . . . . . . . Inside Back CoverUmicore microbond.eu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Westbond westbond.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37This index is provided as a service to advertisers and readers. Chip Scale Review does notassume any liability for errors or omissions in the listings.52Chip Scale Review ■ June 2008 ■ [ChipScaleReview.com]