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Power Architecture (PPC) and ARM compared3 Power Architecture (PPC) and ARM comparedThe Power Architecture has a long history and has been under the control of variousconsortia and companies. There are several standard extensions to the architecture (aswell as several non-standard ones). For this document, we will use the Power 2.03 ISA asdocumented in the Book III-E specification. The term “PPC” will be used to refer to this.For ARM, we will use architecture ARMv7-A as the basis of comparison.Many of the PPC architectural extensions have equivalent elements either in the standardARMv7-A profile or in the extensions to it listed in section 2.2 above.The PPC architecture supports two principle categories: “Server” and “Embedded”. TheServer category supports both 32-bit and 64-bit operating modes, both of which support64-bit registers and address generation. In 32-bit mode, the lower order 32 bits of theresulting address are ignored when accessing memory. The Embedded category alsosupports both 32-bit and 64-bit modes. However, the majority of instructions in 32-bitmode only use and affect the lower order 32 bits of registers.In this document, we only consider the 32-bit Embedded version of the architecture (asdescribed in Book III-E) as this has the clearest correspondence with ARMv7.It is worth noting early on that the PPC architecture is natively big endian, while ARM isnatively little endian. It is important to bear this in mind when reading the documentation ofthe two architectures since bytes within words and also bits within bytes are enumeratedin opposite senses.For instance, the lower 32 bits of a 64-bit register in the PPC architecture are referred toas bits 32 to 63; in the ARM architecture, these would be referred to as bits 0-31. For PPCsystems operating in 32-bit mode, the majority of instructions use the lower 32 bits ofnotionally 64-bit registers. These bits are referred to as bits 32 to 63, with the upper bitsusually being “undefined” except in certain special cases (e.g. double-precision floatingpoint operations).Likewise, ARM refers to the bottom 2 bits of an address as bits 0 and 1; PPC refers tothese as bits 62 and 63. Further, PPC continues to use this numbering even in systemswhich only support 32-bit addressing.3.1 Programmer’s modelBoth PPC and ARM are “RISC” architectures. As such, they have compact instruction setsand large register sets. Both are load-store architectures (i.e. they cannot performcomputation directly on the contents of memory locations).The programmer’s models are therefore somewhat similar since both reflect the RISCapproach. However there are some significant differences.3.1.1 Register setThe PPC architecture supports a comparatively large register set. There are 32 generalpurpose registers, GPR0-GPR31. In the 32-bit embedded category, all of these are 32-bitregisters.There are also a number of special-purpose registers, including:LR – 64-bit Link RegisterLR holds the return address after a branch instruction and can be hold the targetaddress for a Branch Conditional to Link Register instruction.CTR – 64-bit Count RegisterCTR is intended to be used as a general loop counter. CTR can be decrementedautomatically by some branch instructions and can hold target of Branch ConditionApplication Note 245 Copyright © 2012 ARM Limited. All rights reserved. 9ARM DAI 0245B