PDF version - ARM Information Center
PDF version - ARM Information Center
PDF version - ARM Information Center
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<strong>ARM</strong> architecture features4. Exceptions and interrupts<strong>ARM</strong> supports seven basic exception types. External interrupts are mapped to the FIQand IRQ exceptions. Other exceptions are used for external errors (e.g. bus errors),internal errors (e.g. undefined instructions or memory address translation faults), orsoftware interrupts (caused synchronously by executing an SVC instruction).Later <strong>ARM</strong> cores implement a standard Generic Interrupt Controller architecture whichprovides interrupt prioritization, pre-emption, configuration, distribution, masking etc inhardware.<strong>ARM</strong>v7-A cores with the virtualization extensions implement an additional exception (Hyp)which provides entry into a Hypervisor mode which can be used for implementation of afull software hypervisor environment.5. Memory architecture<strong>ARM</strong> cores have a 32-bit address bus providing a flat 4GB linear address space. Memoryis addressed in bytes and may be accessed as 8-byte doublewords, 4-byte words, 2-bytehalfwords or single bytes. Configuration options in the core determine the endianness andalignment behavior of the memory interface.All of the current <strong>ARM</strong>v7-A profile cores provide two-level caching with full virtual memoryaddress translation. In the latest cores, this is extended (in the form of the Large PhysicalAddress Extensions) to provide 40-bit physical addressing (see 2.2.5 above).Cores implementing the multiprocessing extensions (see 2.2.4 above) implementcoherency in the L1 cache across up to four processors in a single multiprocessingcluster.2.4 Debug<strong>ARM</strong> provides debug using the industry-standard JTAG port. As standard, this uses a 5-wire connection. A 2-wire debug port is also available for use in applications where pincountis at a premium.Program trace is provided via a combination additional logic within the chip (EmbeddedTrace Macrocell) and an external Trace Port Adapter unit connected to a Trace Port onthe chip itself.<strong>ARM</strong>’s CoreSight on-chip debug infrastructure allows chip designers to specify and buildcomplex multi-core debug systems which allow synchronous trace and debug of multiplecores within a single device.8 Copyright © 2012 <strong>ARM</strong> Limited. All rights reserved. Application Note 245<strong>ARM</strong> DAI 0245B