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ARM architecture features2.2.4 Multiprocessing2.2.5 40-bit physical addressingThese provide for synchronization and coherency across a “cluster” of processor cores,operating either in Asymmetric or Symmetric Multi-Processing mode. This extension iscurrently supported by the Cortex-A9MP and Cortex-A15 processors.The Large Physical Address Extensions (LPAE) are an optional extension to the ARMv7-Aprofile. It includes an extension to the VMSAv7 virtual memory architecture which allowsthe generation of 40-bit physical addresses from 32-bit virtual addresses.These extensions are currently implemented only in the Cortex-A15 processor.2.2.6 VirtualizationThe virtualization extensions introduce an extra mode (Hypervisor mode) with associatedbanked registers. A new Hyp exception can be used to trap software accesses tohardware and configuration registers, this allowing implementation of a softwarehypervisor.These extensions are currently implemented only in the Cortex-A15 processor.2.3 Programmer’s model2.3.1 Standard featuresThe description presented here is standard for the ARMv7-A and ARMv7-R architectureprofiles. The ARMv7-M microcontroller profile has a different model for modes andexceptions.1. Operating modesThe ARM core supports seven operating modes. All of these, with the exception of Usermode, are privileged. Five modes (Supervisor, Undefined, Abort, FIQ and IRQ) areassociated with handling particular types of exception events. Applications generally runeither in User mode (unprivileged) or System mode (privileged) with the operating system,if one is used, running in Supervisor mode.For ARMv7-A profile cores, the optional virtualization and security extensions introduceanother two modes. These are Hyp, which is intended to support implementation of ahypervisor, and Monitor, which acts as a gatekeeper between the secure and non-secureoperating states.2. Register setThe ARM register set consists of 37 general-purpose registers, 16 of which are usable atany one time. The subset which is usable is determined by the current operation mode(see above).In addition to the general purpose registers, the CPSR (Current Program Status Register)holds current status, operating mode, instruction set state, ALU status flags etc.Five of the operating modes also provide an SPSR (Saved Program Status Register)which is used for taking a copy of processor state on entry to an exception handler.The diagram shows the standard ARMv7-A register set. Where registers are not shownunder a particular mode, the User mode register is used.6 Copyright © 2012 ARM Limited. All rights reserved. Application Note 245ARM DAI 0245B
ARM architecture featuresUser/System FIQ IRQ Abort Undef SVCR0R1R2R3R4R5R6R7R8R9R10R11R12R8R9R10R11R12R13 (SP) R13 (SP) R13 (SP) R13 (SP) R13 (SP) R13 (SP)R14 (LR) R14 (LR) R14 (LR) R14 (LR) R14 (LR) R14 (LR)R15 (PC)CPSRSPSR SPSR SPSR SPSR SPSRIn cores which implement the virtualization and security extensions to the ARMv7-Aprofile, there are extra banked registers associated with Hyp mode and Monitor mode.These are not discussed in this document.3. Instruction setsCurrent ARM cores may support several instruction sets:The native ARM instruction set, in which all instructions are 32-bit.The Thumb instruction set (introduced in ARMv4T), in which all instructions are16-bit. This provides greatly improved code density.Java bytecode – cores which include the Jazelle-DBX extension are capable ofexecuting Java bytecode directly in hardware.The ARM and Thumb instruction sets have both been extended several times sincetheir introduction. In particular, the Thumb-2 extension introduces 32-bit instructionsinto the 16-bit Thumb instruction set providing greatly increased performance withoutcompromising the code density benefits of Thumb.Of the ARM cores available on the market today, all support the ARM and Thumbinstruction sets as a minimum, with the exception of ARMv7-M devices which supportonly the Thumb-2 instruction set.ARMv7-A profile cores also support the ThumbEE extension described in section2.2.3 above.Application Note 245 Copyright © 2012 ARM Limited. All rights reserved. 7ARM DAI 0245B
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