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Migrating a software applicationIt is important to note and obey any guidelines in respect of clearing reservations duringe.g. context switches. ARM provides the CLREX instruction to explicitly clear anyoutstanding reservations.4.9 Accessing peripheralsIn ARM-powered systems, all peripherals are memory-mapped. Implementation andsystem-dependent code is required to define the registers involved and locate them inmemory at the appropriate addresses. These are then accessed using standard memoryaccess instructions.Points to note:Some restrictions on instructions which can be used e.g. LDM/STM should beavoided.Mark peripheral memory regions as Device memory to ensure access ordering isobserved correctly.The PPC architecture, as well as allowing memory-mapped peripherals, also defines anarbitrary number of special purpose registers (DCRs) which can be used to manageperipherals. The number and functionality of these is not defined by the architecture but bythe chip designer. They are accessed using special instructions (mfdcrux and mtdcrux).ARM has no equivalent to this and any ARM-powered devices will have beenimplemented using the standard memory-mapped peripheral mechanism. Any driversoftware which access PPC peripherals using these special purpose registers will needrewriting.4.10 C programmingIn general, the similarities between the two architectures will mean that C code which hasbeen optimized for PPC platforms should perform well when re-compiled for ARM.Clearly any inline assembler or architecturally-specific intrinsic functions will need to beremoved, replaced or rewritten. Similarly, any cache or TLB maintenance code will needto be rewritten. Recall that TLB management in the two architectures is significantlydifferent: in PPC systems, address translation depends on run-time support code topopulate the TLB entries; in ARM systems, the page tables are initialized at startup andthe MMU then reads these at run-time automatically.Both architectures have similarly strict rules on data alignment. However, ARM coressupporting architecture v6 and later are capable of supporting unaligned accesses inhardware. In Cortex-A cores, this feature is permanently enabled; on earlier cores whichsupport backwards compatibility the feature defaults to disabled and can be enabled, ifrequired, by setting the U bit in CP15 register c1.Be careful though with any data which has been declared using special alignmentattributes e.g. the packed attribute. The declaration may need to be corrected to use the__packed keyword when using the ARM tools.32 Copyright © 2012 ARM Limited. All rights reserved. Application Note 245ARM DAI 0245B