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Migrating a software applicationmore detailed description of the power management facilities provided by a typical ARMcore.When using an operating system or real-time scheduler, it is likely that the powermanagement features will have been built into the kernel. In this case, it is simply a caseof ensuring that your user processes make it clear to the scheduler when they are idle.How you do this will be system-dependent.When writing a bare metal application, you will have to insert appropriate instructions intoyour code to allow the hardware to sleep when possible. For instance, busy-wait loopsshould have WFI/WFE instructions inserted. However, it is more power-efficient to avoidpolling in general and implement an interrupt-driven system with power managementinstructions in the main loop.4.8 Semaphores etc.The PPC architecture provides the lwar and stwc instructions for construction ofsemaphores, mutexes etc. The ARM LDREX and STREX instructions operate in a verysimilar way. Both revolve around the concept of a load instruction which “reserves” alocation for a subsequent store instruction which only succeeds if there has been nointervening accesses to the location in question.The major difference is in the means of checking for success of the store instruction.The PPC stwc instruction sets the SO bit in CR0 to indicate success or failure. This bit canbe tested after the instruction. The ARM STREX instruction places its success/failurestatus in a register supplied as an argument to the instruction.The following shows a simple “test-and-set” lock construct implemented in botharchitectures.PPClock:lwarx r5,0,r3cmpwi r5,0bne- exitstwcx. r4,0,r3bne- lockisyncexit: ...unlock:stw r7,data1(r9)mbar 0stw r4,lock(r3)ARMlockLDREX r1, [r0]CMP r1, #LOCKEDBEQ lock_mutexMOV r1, #LOCKEDSTREX r2, r1, [r0CMP r2, #0x0BNE lock_mutexDMBUnlockDMBMOV r1, #UNLOCKEDSTR r1, [r0]Both mechanisms rely on some logic within the memory system for recording the fact thata reservation exists on a particular memory location. The memory system is not requiredto record this at byte or word granularity. Instead, both architectures define the concept ofthe “reservation granule”. It is important to check on the size of the granule when portingas it may be different on the target system – this may result in erroneous operation of lockconstructs when the addresses used are within the boundaries of a single granule.Application Note 245 Copyright © 2012 ARM Limited. All rights reserved. 31ARM DAI 0245B