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Migrating a software applicationstartAREA Vectors, CODE, READONLYIMPORT Reset_Handler; import other exception handlers; …ENTRYLDRLDRLDRLDRLDRNOPLDRpc, Reset_Vectorpc, Undefined_Vectorpc, SWI_vectorpc, Prefetch_Vectorpc, Data_Vectorpc, IRQ_vector; FIQ_Handler can follow directlyReset_Vector DCD Reset_HandlerUndefined_Vector DCD Undefined_Handler; etcENDIn this scheme, the FIQ exception handler may still run from address 0x0000.001C but itis restricted to smaller than 4KB since the table of vector addresses cannot be furtherthan 4KB from the vector table (this is limited by the range of the constant offset in theLDR instructions).If your ARM system incorporates a Vectored Interrupt Controller (the Generic InterruptController, for example), the IRQ entry in the vector table is not used. Instead the core isprovided with the address of the interrupt handler for the active interrupt automatically bythe interrupt controller and branches directly to that routine. This routine must still bewritten following the IRQ handler conventions regarding context saving, register usage, reentrancyand return instruction.4.5.3 Interrupt configurationIn an ARM system, interrupts (external physical events) and exceptions (internal events)are configured slightly differently. Exceptions (i.e. Undefined Instruction, SVC, PrefetchAbort, Data Abort) are always enabled (though imprecise aborts can be disabled onARMv7 cores). IRQ and FIQ must be enabled by clearing the I and F bits respectively inCPSR.If an interrupt controller (e.g. ARM’s Generic Interrupt Controller) is being used on anARM system, the configuration will be required to at least enable and prioritize the externalinterrupt sources before they can be used.4.6 Timing and delays4.7 Power ManagementARM cores do not provide a standard timer function as part of the architecture (ARMv7-Mcores do provide the SysTick peripheral). However, almost all ARM-based devices willinclude a generic timer facility. Some ARMv7-A cores, particularly those implementing themulti-processing extensions, do provide a system timer as part of the interrupt controller –this time is common to all the cores in a cluster.The power management options in an ARM-based device are likely to be more varied andmore standardized than those available with a PPC device. See section 3.6 above for a30 Copyright © 2012 ARM Limited. All rights reserved. Application Note 245ARM DAI 0245B
Migrating a software applicationmore detailed description of the power management facilities provided by a typical ARMcore.When using an operating system or real-time scheduler, it is likely that the powermanagement features will have been built into the kernel. In this case, it is simply a caseof ensuring that your user processes make it clear to the scheduler when they are idle.How you do this will be system-dependent.When writing a bare metal application, you will have to insert appropriate instructions intoyour code to allow the hardware to sleep when possible. For instance, busy-wait loopsshould have WFI/WFE instructions inserted. However, it is more power-efficient to avoidpolling in general and implement an interrupt-driven system with power managementinstructions in the main loop.4.8 Semaphores etc.The PPC architecture provides the lwar and stwc instructions for construction ofsemaphores, mutexes etc. The ARM LDREX and STREX instructions operate in a verysimilar way. Both revolve around the concept of a load instruction which “reserves” alocation for a subsequent store instruction which only succeeds if there has been nointervening accesses to the location in question.The major difference is in the means of checking for success of the store instruction.The PPC stwc instruction sets the SO bit in CR0 to indicate success or failure. This bit canbe tested after the instruction. The ARM STREX instruction places its success/failurestatus in a register supplied as an argument to the instruction.The following shows a simple “test-and-set” lock construct implemented in botharchitectures.PPClock:lwarx r5,0,r3cmpwi r5,0bne- exitstwcx. r4,0,r3bne- lockisyncexit: ...unlock:stw r7,data1(r9)mbar 0stw r4,lock(r3)ARMlockLDREX r1, [r0]CMP r1, #LOCKEDBEQ lock_mutexMOV r1, #LOCKEDSTREX r2, r1, [r0CMP r2, #0x0BNE lock_mutexDMBUnlockDMBMOV r1, #UNLOCKEDSTR r1, [r0]Both mechanisms rely on some logic within the memory system for recording the fact thata reservation exists on a particular memory location. The memory system is not requiredto record this at byte or word granularity. Instead, both architectures define the concept ofthe “reservation granule”. It is important to check on the size of the granule when portingas it may be different on the target system – this may result in erroneous operation of lockconstructs when the addresses used are within the boundaries of a single granule.Application Note 245 Copyright © 2012 ARM Limited. All rights reserved. 31ARM DAI 0245B
Page 1 and 2: Application Note245Migrating from P
Page 3 and 4: IntroductionTable of Contents1 Intr
Page 5 and 6: ARM architecture features2 ARM arch
Page 7 and 8: ARM architecture featuresUser/Syste
Page 9 and 10: Power Architecture (PPC) and ARM co
Page 25 and 26: Migrating a software application4 M
Page 27 and 28: 4.2 Tools configurationMigrating a
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Page 33 and 34: A porting checklist5 A porting chec

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