PDF version - ARM Information Center
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Migrating a software applicationstartAREA Vectors, CODE, READONLYIMPORT Reset_Handler; import other exception handlers; …ENTRYLDRLDRLDRLDRLDRNOPLDRpc, Reset_Vectorpc, Undefined_Vectorpc, SWI_vectorpc, Prefetch_Vectorpc, Data_Vectorpc, IRQ_vector; FIQ_Handler can follow directlyReset_Vector DCD Reset_HandlerUndefined_Vector DCD Undefined_Handler; etcENDIn this scheme, the FIQ exception handler may still run from address 0x0000.001C but itis restricted to smaller than 4KB since the table of vector addresses cannot be furtherthan 4KB from the vector table (this is limited by the range of the constant offset in theLDR instructions).If your <strong>ARM</strong> system incorporates a Vectored Interrupt Controller (the Generic InterruptController, for example), the IRQ entry in the vector table is not used. Instead the core isprovided with the address of the interrupt handler for the active interrupt automatically bythe interrupt controller and branches directly to that routine. This routine must still bewritten following the IRQ handler conventions regarding context saving, register usage, reentrancyand return instruction.4.5.3 Interrupt configurationIn an <strong>ARM</strong> system, interrupts (external physical events) and exceptions (internal events)are configured slightly differently. Exceptions (i.e. Undefined Instruction, SVC, PrefetchAbort, Data Abort) are always enabled (though imprecise aborts can be disabled on<strong>ARM</strong>v7 cores). IRQ and FIQ must be enabled by clearing the I and F bits respectively inCPSR.If an interrupt controller (e.g. <strong>ARM</strong>’s Generic Interrupt Controller) is being used on an<strong>ARM</strong> system, the configuration will be required to at least enable and prioritize the externalinterrupt sources before they can be used.4.6 Timing and delays4.7 Power Management<strong>ARM</strong> cores do not provide a standard timer function as part of the architecture (<strong>ARM</strong>v7-Mcores do provide the SysTick peripheral). However, almost all <strong>ARM</strong>-based devices willinclude a generic timer facility. Some <strong>ARM</strong>v7-A cores, particularly those implementing themulti-processing extensions, do provide a system timer as part of the interrupt controller –this time is common to all the cores in a cluster.The power management options in an <strong>ARM</strong>-based device are likely to be more varied andmore standardized than those available with a PPC device. See section 3.6 above for a30 Copyright © 2012 <strong>ARM</strong> Limited. All rights reserved. Application Note 245<strong>ARM</strong> DAI 0245B