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Migrating a software applicationThe operating system initialization code should ensure that at least the following arecarried out:1. Enable branch prediction2. Initialize exception and application stack pointer3. Initialize page tables, enable caches and MMU4. Execute main program4.5 Handling interrupts and exceptions4.5.1 Writing interrupt handlersAn ARM system usually requires at least two interrupt handlers: IRQ and FIQ.Typically, a single interrupt source (that with the lowest latency requirement) is connectedto FIQ. FIQ interrupts are not normally nested. At least a simple top-level FIQ handlermust be written in assembler though this will usually call out to a C function to handle theinterrupt before returning, via the assembler, to the interrupted application.The ARM tools support writing simple (i.e. non-reentrant) IRQ handlers directly in C. Forsimple systems, this is a useful feature. However, most systems require re-entrantinterrupts. This requires a small top-level IRQ handler in assembler which then calls out toa C function to dispatch to the correct handler before return, via the assembler, to theinterrupted application.The implementation of the assembler part of the handler is shown below. Note that thiscode will not be suitable for architectures prior to ARMv6.Non-nested IRQ handler (v6 and later)IRQ_HandlerPUSH {r0-r3, r12, lr}BL identify_and_clear_sourceBL C_irq_handlerPOP {r0-r3, r12, lr}SUBS pc, lr, #4Nested IRQ handler (v6 and later)IRQ_HandlerSUB lr, lr, #4SRSFD sp!, #0x1fCPS#0x1fPUSH {r0-r3, r12}AND r1, sp, #4SUB sp, sp, r1PUSH {r1, lr}BLidentify_and_clear_sourceCPSIE iBLC_irq_handlerCPSID iPOPADD{r1, lr}sp, sp, r1POP {r0-r3, r12}RFEFD sp!The nested IRQ handler re-enables IRQ interrupts (using the CPSIE instruction).However, before doing this, to prevent corruption of the return address, it must change to28 Copyright © 2012 ARM Limited. All rights reserved. Application Note 245ARM DAI 0245B