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Power Architecture (PPC) and <strong>ARM</strong> comparedPPC <strong>ARM</strong> MnemonicicbiN/AN/AdcbiN/Adcbf(Cleaning as part ofinvalidation isimplementation-defined)N/Adcbfl(Cleaning as part ofinvalidation isimplementation-defined)dcbf(Cleaning as part ofinvalidation isimplementation-defined)N/AInstruction cache to PoUInvalidate Branch Predictorarray Inner ShareableInvalidate all instructioncaches to PoUInvalidate I cache by MVA toPoUInvalidate Branch PredictorarrayInvalidate Branch Predictorarray by MVAInvalidate data/unified cacheby MVA to PoCInvalidate data/unified cacheby set/wayClean data/unified cache lineby MVA to PoCClean data/unified cache lineby set/wayClean data/unified cache lineto PoU by MVAClean and Invalidatedata/unified cache line byMVA to PoCClean and Invalidatedata/unified cache line byset/wayBPIALLISICIALLUICIMVAUBPIALLBPIMVADCIMVACDCISWDCCMVACDCCSWDCCMVAUDCCIMVACDCCISWIt is clear that the set of cache maintenance operations provided by <strong>ARM</strong> is morecomprehensive and more flexible. <strong>ARM</strong>, however, provides no matching instructions fordcba, dcbz and dcbst. PLI and PLD perform similar functions to the PPC icbt and dcbtinstructions.“Point of Unification (PoI)” and “Point of Coherency (PoC)” are terms which have specificmeaning when referred to shared memory within <strong>ARM</strong> systems. Refer to the <strong>ARM</strong>Architecture Reference Manual for the precise definitions of these terms.3.5 DebugBoth architectures provide for debug over the standard JTAG connections. The underlyingimplementation, however, is rather different.PPC devices support a dedicated debug interrupt and a set of debug status/configurationregisters (within the set of SPRs). These are used by external debug agents to provide22 Copyright © 2012 <strong>ARM</strong> Limited. All rights reserved. Application Note 245<strong>ARM</strong> DAI 0245B