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Power Architecture (PPC) and ARM compared3.4.5 AtomicityBoth architectures define that only byte, aligned halfword and aligned word accesses areguaranteed atomic. Other accesses (e.g. an access to an unaligned word) should beregarded as non-atomic in the sense that part of the memory content may be accessedbefore the instruction is abandoned and then this access will be repeated or restarted.3.4.6 Barriers and synchronizationThere are cases in program execution where it is necessary or desirable to ensure thatcertain classes of memory access are completed in a certain order.The ARM system of memory typing (in which memory is defined as “Normal”, “Device” or“Strongly Ordered”) ensures that this is the case in the vast majority of circumstances.However, there may be cases where the program need to explicitly ensure ordering.The following table indicates the ARM instructions corresponding to the barrierinstructions defined by the PPC architecture.PPCisyncsync (msyuc/hwsync)lwsyncptesynceieiombar(identical to the eieio instruction in earlierPPC architectures)ARMIMBInstruction Memory BarrierDMBData Memory BarrierDMBData Memory BarrierDSBData Synchronization Barrier (whenchanging MMU context, in which case notethat an IMB may also be required)N/AThe default rules for Device memory aregenerally sufficient, though a DMB may berequired in some circumstances e.g. toenforce ordering between device accesseswhich are in different regions of Devicememory.N/AThough see the notes for eieio above.As stated in the table, the PPCeieio instruction can usually be omitted in correspondingARM code.eieio is used primarily for enforcing access ordering when dealing withmemory-mapped devices and, on ARM systems, the rules associated with Devicememory are generally sufficient to remove the need for a barrier in these circumstances.However, you should examine carefully any cases whereeieio has been used incacheable memory on PPC systems. In this situation, aDMB may be required in theequivalent ARM code.Additionally, both architectures define sets of instructions which can be used to implementcommon synchronization or exclusion sequences.20 Copyright © 2012 ARM Limited. All rights reserved. Application Note 245ARM DAI 0245B