PDF version - ARM Information Center
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Power Architecture (PPC) and <strong>ARM</strong> comparedPPC<strong>ARM</strong>Name Location Function Name LocationFE1 MSR[55] Floating PointExceptionMode 1?? See FE0 aboveIS MSR[58] InstructionAddressSpaceDS MSR[59] Data AddressSpacePMM MSR[61] PerformanceMonitor MarkN/AN/AN/AThe two addressspaces in PPC areanalogous to<strong>ARM</strong>’s dual pagetable system<strong>ARM</strong>’sPerformanceMonitor does notprovide thisfeature3.1.3 Instruction setIn the PPC architecture, instructions are classified as Branch, Fixed-Point or Floating-Point. There are additional classifications associated with extensions such as SignalProcessing, Vector etc.Broadly, the Fixed-Point instructions correspond to the set of <strong>ARM</strong> instructions which carryout ALU operations, together with Load and Store instructions; the Floating-Pointinstructions correspond to <strong>ARM</strong>’s VFP and NEON instructions.The following terms are also used when describing PPC architecture instructions:PPCFixed-PointRecordAlgebraicLogical<strong>ARM</strong>IntegerSet condition codesSignedUnsigned (in comparison instructions)This table shows some example equivalent instructions in the two architectures.PPC<strong>ARM</strong>addi %r0, %r1, 2 ADD r0, r1, #2lwzux %r0, %r1, %r2 LDR r0, [r1, r2]!bdnzlrBXNE lrPPC branch instructions always set LR to the address of the next instruction regardless ofwhether the branch is taken or not. This is done at the time that the branch destinationaddress is calculated. This differs from the <strong>ARM</strong> behavior, in which the link register (lr) isonly set if the branch is taken. PPC branch instructions also include “hint” bits which can12 Copyright © 2012 <strong>ARM</strong> Limited. All rights reserved. Application Note 245<strong>ARM</strong> DAI 0245B