2002 - cesnet

have already discussed some possibilities, e.g., within the SCAMPI project oroptical network testing.At first, we are planning to design a communication interface card with 4 ports,using the usual communication circuits for Gigabit Ethernet 1000BASE-T (metalliccables of category 5). This will be followed by a card with four optical interfacesand VIRTEX II PRO circuits. Optical transceivers will be installed in SFPcages and so their replacement with another type (single-mode or multimodefibres with various wavelengths, possibly also with WDM) will be very simple.At present, the basic draft of the COMBO6 motherboard is complete, the printedcircuit board has been produced and the card has been populated – see Figure5.3.Firmware for COMBO6 CardFor the purposes of programming the gate array firmware, we make use of theVHDL language. The development system of VHDL also includes the LeonardoSpectrum translator and ModelSim simulator produced by Mentor Graphics.Our objective is to enable a wider community than just the project team toparticipate in the development. Most potential contributors may find the highexpenses on the acquisition of VHDL development system unacceptable. Wetherefore introduced an abstraction in the form of logical functional blocksrealized inside FPGA, which we call nanoprocessors. These represent a transitionbetween programmable state automata and microprocessor cores, haveonly few instructions and the length of their “nanoprograms” does not exceedseveral dozens of instructions. We expect that these “nanoprograms” may alsobe modified by external developers, without access to the VHDL developmentsystem.The designed firmware for packet switching in the COMBO6 board includes thefollowing functional blocks (see also Figure 5.4):• Input packet buffer memory (IPB)• L2 and L3 header field extractor (HFE),• Look-up processor (LUP),• Packet replicator and block of output queues (RQU),• Output packet editor (OPE),• Output packet buffer (OPB),• PCI interface (PCI),• Dynamic memory controller (DRAM)After being accepted and processed, packets are stored in IPB, and proceed tothe HFE block, where information necessary for routing and packet filtering areextracted. The data content of the packet is then stored in a dynamic memory.The HFE, LUP and OPE blocks are realized by nanoprocessors.74 High-speed National Research Network and its New Applications 2002