Interfacing a Hantronix 128x64 Graphic Module to an 8-bit ...
Interfacing a Hantronix 128x64 Graphic Module to an 8-bit ...
Interfacing a Hantronix 128x64 Graphic Module to an 8-bit ...
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Application NoteCrystalClear<strong>an</strong>dVisiblySuperior LCD<strong>Module</strong>s<strong>Interfacing</strong> a<strong>H<strong>an</strong>tronix</strong> <strong>128x64</strong> <strong>Graphic</strong> <strong>Module</strong><strong>to</strong> <strong>an</strong> 8-<strong>bit</strong>MicrocontrollerIntroduction:Due <strong>to</strong> its thin profile, light weight, low power consumption <strong>an</strong>d easy h<strong>an</strong>dling, liquid crystal graphic displaymodules are used in awide variety of applications. This note details asimple interface technique between a<strong>H<strong>an</strong>tronix</strong> HDM64GS12 <strong>an</strong>d amicro-controller. The HDM64GS12 has abuilt-in Hitachi HD61202, or SamsungKS107, controller which performs all of the refreshing <strong>an</strong>d data s<strong>to</strong>rage tasks of the LCD display. This noteapplies <strong>to</strong> <strong>an</strong>y display using these controllers. The driving micro-controller is the popular 87C751.The display is split logically in half. It contains two controllers with controller #1 (Chip select 1) controlling th eleft half of the display <strong>an</strong>d controller #2 (Chip select 2) controlling the right half. Each controller must beaddressed independently.The page addresses, 0-7, specify one of the 8horizontal pages which are 8<strong>bit</strong>s (1 byte) high. Adrawing of thedisplay <strong>an</strong>d how it is mapped <strong>to</strong> the refresh memory is shown below.Controller #1 CS1=1, CS2=0Controller #2 CS1=0, CS2=1D0D1D2D3D4D5D6D7PAGE 0 64 bytes (columns) x8<strong>bit</strong>sPAGE 1PAGE 2PAGE 3PAGE 4PAGE 0PAGE 1PAGE 2PAGE 3PAGE 464bItsPAGE 5PAGE 5PAGE 6PAGE 6PAGE 7PAGE 764 <strong>bit</strong>s 64 <strong>bit</strong>sThe schematic on page two is asimple circuit <strong>to</strong> illustrate one possible interface scheme. This is the circuit thatthe code example will work with directly.Page 1
Application NoteCrystalClear<strong>an</strong>dVisiblySuperior LCD<strong>Module</strong>sSoftware Source Code:$MOD751;**************************************************;* *;* HD61202 Application Note V1.0 *;* *;**************************************************;The processor clock speed is 16MHz.;Cycle time is .750mS.;HD61202 demo software <strong>to</strong> display;the <strong>H<strong>an</strong>tronix</strong> logo on a128 x64 LCD.orgljmporg00hstart100h;Initialize the 64gs12Start:mov p3,#00mov r0,#00h ;set 64gs12 leftmov dptr,#msgi1 ;initialization byteslcall comm<strong>an</strong>dmov r0,#01h ;set 64gs12 rightmov dptr,#msgi1 ;initialization byteslcall comm<strong>an</strong>d;Display patternmov r4,#0b8h ;page comm<strong>an</strong>dmov r5,#08h; ;page countLoop1:mov r0,#00h ;set 64gs12 leftmov dptr,#msg1llcall byteclr p3.1 ;set comm<strong>an</strong>dinc r4 ;bump page addmov a,r4mov r1,alcall writedjnz r5,loop1 ;repeat 8timesmov r4,#0b8h ;page add. Comm<strong>an</strong>dmov r5,#8h ;page countLoop2:mov r0,#01h ;set 64gs12 rightmov dptr,#msg1rlcall byteclr p3.1 ;set comm<strong>an</strong>dinc r4 ;bump page addmov a,r4mov r1,alcall writedjnz r5,loop2 ;repeat 8timessjmp $ ;end;*************************************************;SUBROUTINES;COMMAND sends the byte pointed <strong>to</strong> by;the DPTR <strong>to</strong> the graphics module;as aseries of comm<strong>an</strong>ds.Comm<strong>an</strong>d:clr p3.1 ;set comm<strong>an</strong>dComm<strong>an</strong>d2:clr amovc a,@a+dptr ;get bytecjne a,#099h,comm<strong>an</strong>d1 ;done?RetComm<strong>an</strong>d1:mov r1,alcall write ;send itinc dptrsjmp comm<strong>an</strong>d2;BYTE sends the byte pointed <strong>to</strong> by;the DPTR <strong>to</strong> the graphics module;as aseries of data bytes.Byte:setb p3.1 ;set datasjmp comm<strong>an</strong>d2;WRITE sends the byte in R1 <strong>to</strong> the;display.Write:mov a,r0 ;CS the displayjnz write1 ;right halfsetb p3.2 ;left halfWrite2:mov p1,r1 ;get datasetb p3.0 ;strobe itNopclr p3.0clr p3.2 ;de-select moduleclr p3.3RetWrite1:setb p3.3sjmp write2Page 4
Application NoteCrystalClear<strong>an</strong>dVisiblySuperior LCD<strong>Module</strong>s;************************************************;TABLES AND DATA;Initialization bytesMsgi1:db 0c0h,40h,0b8h,3fh,99h;"<strong>H<strong>an</strong>tronix</strong>", left halfMsg1l:db 0,0feh,10h,10h,10h,0feh,0 ;Hdb 0fch,12h,12h,12h,0fch,0 ;Adb 0feh,08h,10h,20h,0feh,0 ;Ndb 02h,02h,0feh,02h,02h,0 ;Tdb 0feh,12h,32h,52h,8ch,0 ;Rdb 7ch,82h,82h,82h,7ch,0 ;Odb 0feh,08h,10h,20h,0feh,0 ;Ndb 0,0,82h,0feh,82h,0 ;Idb 0,0c6h,28h,10h,28h,0c6h,0 ;Xdb 0,38h,7ch,0f8h,7ch,38h,0 ;heartdb 0,99h;"<strong>H<strong>an</strong>tronix</strong>", right half (reverse video)Msg1r:db 0ffh,0c7h,83h,07h,83h,0c7h,0ffh ;heartdb 0 ffh,39h,0d7h,0efh,0d7h,39h,0ffh ;Xdb 0ffh,0ffh,7dh,01h,7dh,0ffh ;Idb 01h,0dfh,0efh,0f7h,01h,0ffh ;Ndb 83h,7dh,7dh,7dh,83h,0ffh ;Odb 073h,0adh,0cdh,0edh,01h,0ffh ;Rdb 0fdh,0fdh,01h,0fdh,0fdh,0ffh ;Tdb 01h,0dfh,0efh,0f7h,01h,0ffh ;Ndb 03h,0edh,0edh,0edh,03h,0ffh ;Adb 0ffh,01h,0efh,0efh,0efh,01h,0ffh ;Hdb 0ffh,99hendPage 5
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