A Variable Output Power, High Efficiency, Power Amplifier for the ...

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efficiency the transistors are biased towards class B operation.The amplifier was designed for a drain supply (V D ) of 28V.A. Design ProcedureLarge-signal models were available for both transistorsfrom the manufacturers. Although their validity could bequestioned they were later shown to well model the behaviourunder the conditions used in this design. Initially harmonicbalance,load-pull simulations were conducted in Agilent-ADS to establish a high power added efficiency (PAE) at therequested output power for the power stage. The trade-offbetween output power, gain, efficiency and quiescent pointwas observed in the simulations and an optimal quiescentcurrent of around 10 % and 5 % of the maximum saturateddrain current for both power and driver stage respectivelywere determined to achieve the desired objectives of outputpower and efficiency. Independent load and source-pullsimulations were then performed for both stages. Initially,load and source-pull simulations were performed with idealcomponents and ideal optimum load and source impedanceswere found. Independently both transistors were stabilized tounconditional stability by fulfilling the Rollet’s stabilitycriterion [8] (K > 1). This was achieved by adding a parallelresistance with capacitance in series at the input, effectivelyreducing the low frequency gain. λ/4 transmission lines wereused in the biasing networks to improve isolation at RFfrequency. Load and source pull simulation were performedagain to achieve optimum impedances for the two stages. Theoptimum load and source impedances found are summarizedTable I. A maximum optimum driver stage quiescent current(IDQ (DS) ) was found to be 32 mA at an optimum power stagequiescent current (IDQ (PS) ) of 123 mA.TABLE IOPTIMUM LOAD AND SOURCE IMPEDANCE AND QUIESSENTCURRENTPower stage(PS)Driver stage(DS)Z LOAD[]Z SOURCE[]I DQ[mA]6.2 – j10.3 6.7 – j26.5 1236.0 – j6.6 5.0 – j30.0 32B. Design ImplementationThe matching networks were realized using micro-striplines together with open stubs in low pass form. Inputmatching was designed to achieve good return loss. It wasimplemented using a tapered line to compensate for some ofthe series capacitance introduces by the capacitor in thestabilizing network. The inter-stage matching network wasdesigned to minimize mismatch losses and for maximumtransfer of power between the two stages. The outputmatching network was designed for minimum loss to the loadand a simulated insertion loss < 0.1 dB was achieved for afrequency range of 200 MHz with centre frequency of2.45 GHz. Momentum simulations were used to verify theimpedances created by the linear matching networks.C. Design RealizationThe amplifier was built on Rogers RO4003 substrate with adielectric constant ε r of 3.66 and thickness of 0.51 mm. Fig. 2shows a prototype for the designed PA.Fig. 2 Power amplifier prototypeVia holes were manually fabricated. Thermal control wasestablished using an aluminium heat sink with a cooling fan.Bias was separately controllable for the two stages in theinitial tests but was later fixed for the power stage andintegrated with a temperature-gain control circuitry. Thematching networks were made on separate substrates so thatlinear performance of the networks could be measured andverified individually.III. AMPLIFIER EVALUATIONThe design process was totally based on a model approach.Small signal evaluation was therefore used to verify thecorrectness of the models used thereby validating the designprocess.A. Small Signal PerformanceThe small-signal s-parameters of the full amplifier are showin Fig. 3.S-Parameters [dB]40200-20-40S21simS11simS22simS21measS22measS11meas2.0 2.2 2.4 2.6 2.8 3.0ƒ [GHz]Fig. 3 Measured and simulated small signal s-parameters at V D = 28 V andmaximum drain current for the driver stage.It can be observed that a small-signal gain of 27 dB withinput and output reflections less than -15 dB in the operatingfrequency is achieved. The K factor was measured to > 4 overthe frequency band from 1 kHz – 10 GHz. This is mainlybecause both the stages were individually stabilized beforecascading. Compared to simulations, gain measurements2009 SBMO/IEEE MTT-S International Microwave & Optoelectronics Conference (IMOC 2009) 822
exhibit some degradation although the main behaviour is verywell tracked by the simulations. The small discrepancy is acombination of many factors, transistor model in-accuracy,tolerance of the used devices and tolerance in the fabricatedboards.B. Power Performance at Maximum BiasA signal generator together with a pre-amplifier was usedas power source in order to generate desired maximumavailable input power (P AVS ) of 20 dBm during the powermeasurements. Initially the maximum operating performancewas tested at maximum driver stage biasing, I DQ(DS) = 32 mA.The measured results of output power, transducer power gain(Gain), drain efficiency and power added efficiency are shownin Fig. 4 and Fig. 5.P OUT[dBm], Gain [dB]50403020Gainsim [dB] Gainmeas[dB]Poutsim [dBm] Poutmeas [dBm]105 10 15 20 25Fig. 4 Measured and simulated gain and output power performance at V D =28 V, I DQ(DS) = 23 mA and I DQ(PS) = 123 mA.80C. Power Performance over BandwidthAlthough the amplifier was designed for a fixed frequencyuse at 2.45 GHz the ISM band allows some frequencymodulation of the signals. The amplifier was thereforemeasured over a limited bandwidth around the designfrequency. Fig. 6 shows the power performance at saturationover a 150 MHz frequency range.PA Performance806040200Gainsim [dB] Gainmeas [dB]PAEsim [%] PAEmeas [%]Poutsim [dBm] Poutmeas [dBm]2.35 2.40 2.45 2.50ƒ [GHz]Fig. 6 Output power and PAE for a frequency range of 150 MHz at V D = 28V, I DQ(DS) = 23 mA and I DQ(PS) = 123 mA.An output power of more than 29 W and a PAE of morethan 60 % could be measured over the full 150 MHzbandwidth. Very good agreement was also found over theband between simulated and measured results.D. Power Performance over Gain ControlThe gain of the amplifier is controlled by setting the gatevoltage of the driver stage LDMOS thereby adjusting I DQ(DS) .Fig. 7 shows the output power controllability of the amplifier.46Efficiency [%]604020P OUT[dBm]4442sim [%] PAEsim [%]meas [%] PAEmeas [%]05 10 15 20 25Input PowerdBmFig. 5 Measured and simulated drain efficiency and PAE at V D = 28 V, I DQ(DS)= 23 mA and I DQ(PS) = 123 mA.A saturated output power of 44.8 dBm (30 W) and a gain of25 dB was achieved. The maximum drain efficiency is 67.8 %at saturated power along with an almost similar PAE due tothe high gain of the amplifier. Very good agreement betweensimulation and measurements were observed.40P OUT(meas)P OUT(sim)380 10 20 30 40IDS_Driver [mA]Fig. 7 Measured and simulated power control at f = 2.45 GHz. V D = 28 V,and I DQ(PS) = 123 mA.As shown the controllability tracks very well the simulatedvalues. By varying the current of the driver stage between3 mA and 33 mA at a constant input power (P IN ) at 100 mW(20 dBm) a measured tuneable range of 5 dB was achieved2009 SBMO/IEEE MTT-S International Microwave & Optoelectronics Conference (IMOC 2009) 823
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