- Page 1 and 2: Cortex -A8Revision: r2p2Technical R
- Page 3 and 4: Product StatusThe information in th
- Page 5 and 6: ContentsCortex-A8 Technical Referen
- Page 7: Contents7.8 Parity detection ......
- Page 11 and 12: List of TablesCortex-A8 Technical R
- Page 14 and 15: List of TablesTable 3-103 Results o
- Page 16 and 17: List of TablesTable 12-1 Access to
- Page 18 and 19: List of TablesTable 15-3 CTI regist
- Page 20 and 21: List of Tablesxx Copyright © 2006-
- Page 22 and 23: List of FiguresFigure 3-10 Memory M
- Page 24 and 25: List of FiguresFigure 10-13 Retenti
- Page 26 and 27: List of FiguresFigure 15-16 CTI Cha
- Page 28 and 29: PrefaceAbout this manualThis is the
- Page 30 and 31: PrefaceChapter 16 Instruction Cycle
- Page 32 and 33: PrefacePrefix CPrefix HPrefix nPref
- Page 34 and 35: PrefaceFeedbackARM welcomes feedbac
- Page 36 and 37: Introduction1.1 About the processor
- Page 38 and 39: Introduction1.3 Components of the p
- Page 40 and 41: Introduction1.3.4 Load/storeThe loa
- Page 42 and 43: Introduction1.4 External interfaces
- Page 44 and 45: Introduction1.6 Power managementThe
- Page 46 and 47: Introduction1.8 Product revisionsTh
- Page 48 and 49: Introduction1-14 Copyright © 2006-
- Page 50 and 51: Programmer’s Model• Hardware co
- Page 52 and 53: Programmer’s Model2.2 Thumb-2 ins
- Page 54 and 55: Programmer’s Model2.3 ThumbEE ins
- Page 56 and 57: Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
- Page 64 and 65:
Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
- Page 68 and 69:
Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
- Page 94 and 95:
Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control CoprocessorTable 3-3
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System Control CoprocessorTable 3-3
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System Control CoprocessorTable 3-3
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System Control CoprocessorTable 3-3
- Page 114 and 115:
System Control CoprocessorTable 3-3
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System Control CoprocessorTable 3-3
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System Control CoprocessorTable 3-3
- Page 120 and 121:
System Control CoprocessorTable 3-3
- Page 122 and 123:
System Control CoprocessorTable 3-5
- Page 124 and 125:
System Control CoprocessorThe TCM T
- Page 126 and 127:
System Control CoprocessorTable 3-1
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System Control CoprocessorFigure 3-
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System Control CoprocessorTable 3-1
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System Control CoprocessorTable 3-1
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System Control CoprocessorTable 3-2
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System Control CoprocessorTable 3-2
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System Control Coprocessor31 28 27
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System Control CoprocessorTable 3-2
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System Control CoprocessorTable 3-3
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System Control CoprocessorTable 3-3
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System Control CoprocessorTable 3-3
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System Control Coprocessor3.2.20 c0
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System Control Coprocessor31 24 23
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System Control CoprocessorTable 3-4
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System Control Coprocessora. An ent
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System Control CoprocessorTable 3-4
- Page 158 and 159:
System Control CoprocessorThe Auxil
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System Control CoprocessorBits Fiel
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System Control CoprocessorBits Fiel
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System Control Coprocessora. n is t
- Page 166 and 167:
System Control CoprocessorTable 3-5
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System Control CoprocessorFigure 3-
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System Control CoprocessorBits Fiel
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System Control CoprocessorBits Fiel
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System Control CoprocessorBits Fiel
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System Control CoprocessorTable 3-6
- Page 178:
System Control CoprocessorBits Fiel
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System Control CoprocessorMRC p15,
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System Control Coprocessor3.2.37 c5
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System Control CoprocessorTable 3-7
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System Control CoprocessorTable 3-7
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System Control CoprocessorTable 3-7
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System Control CoprocessorTable 3-7
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System Control CoprocessorVA to PA
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System Control CoprocessorTable 3-8
- Page 197 and 198:
System Control CoprocessorInvalidat
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System Control CoprocessorThe PMNC
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System Control CoprocessorCWhen wri
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System Control CoprocessorTable 3-8
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System Control Coprocessor3.2.47 c9
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System Control CoprocessorMRC p15,
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System Control CoprocessorTable 3-9
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System Control CoprocessorTable 3-9
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System Control Coprocessorb. The EN
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System Control CoprocessorCWhen rea
- Page 217 and 218:
System Control CoprocessorTable 3-1
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System Control CoprocessorTable 3-1
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System Control Coprocessor• acces
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System Control CoprocessorBits Fiel
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System Control CoprocessorYou can c
- Page 227 and 228:
System Control CoprocessorIf the op
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System Control Coprocessor31 20 19
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System Control CoprocessorTable 3-1
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System Control CoprocessorTo access
- Page 235 and 236:
System Control CoprocessorTable 3-1
- Page 237 and 238:
System Control Coprocessora. An ent
- Page 239 and 240:
System Control Coprocessor3.2.62 c1
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System Control CoprocessorTable 3-1
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
- Page 247 and 248:
System Control CoprocessorTable 3-1
- Page 249 and 250:
System Control CoprocessorTable 3-1
- Page 251 and 252:
System Control CoprocessorTable 3-1
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System Control CoprocessorMRC p15,
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System Control Coprocessor31 25 24
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System Control Coprocessor3.2.72 c1
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System Control CoprocessorTable 3-1
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System Control CoprocessorFigure 3-
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System Control CoprocessorTo perfor
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System Control Coprocessor3.2.75 c1
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System Control CoprocessorLDR R1, =
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
- Page 277 and 278:
System Control CoprocessorTable 3-1
- Page 279 and 280:
System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
- Page 283 and 284:
Chapter 4Unaligned Data and Mixed-e
- Page 285 and 286:
Unaligned Data and Mixed-endian Dat
- Page 287 and 288:
Unaligned Data and Mixed-endian Dat
- Page 289 and 290:
Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
- Page 293 and 294:
Program Flow Prediction5.2.1 Return
- Page 295 and 296:
Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
- Page 301 and 302:
Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
- Page 309 and 310:
Level 1 Memory System7.2 Cache orga
- Page 311 and 312:
Level 1 Memory System7.3 Memory att
- Page 313 and 314:
Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
- Page 317 and 318:
Level 1 Memory SystemAn exception t
- Page 319 and 320:
Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
- Page 323 and 324:
Level 2 Memory System8.2 Cache orga
- Page 325 and 326:
Level 2 Memory System8.3 Enabling a
- Page 327 and 328:
Level 2 Memory SystemControl Regist
- Page 329 and 330:
Level 2 Memory System8.4.4 Memory r
- Page 331 and 332:
Level 2 Memory System8.5 Synchroniz
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Level 2 Memory System8.6 Locked acc
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Chapter 9External Memory InterfaceT
- Page 337 and 338:
External Memory Interfaceto the wri
- Page 339 and 340:
External Memory InterfaceTable 9-2
- Page 341 and 342:
External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
- Page 345 and 346:
External Memory InterfaceTable 9-6
- Page 347 and 348:
External Memory InterfaceTable 9-6
- Page 349 and 350:
External Memory InterfaceTable 9-6
- Page 351 and 352:
External Memory InterfaceTable 9-7
- Page 353 and 354:
Chapter 10Clock, Reset, and Power C
- Page 355 and 356:
Clock, Reset, and Power Controlfami
- Page 357 and 358:
Clock, Reset, and Power Control10.2
- Page 359 and 360:
Clock, Reset, and Power Control•
- Page 361 and 362:
Clock, Reset, and Power Control2. F
- Page 363 and 364:
Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control•
- Page 369 and 370:
Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlThe
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlTo p
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlATBI
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Clock, Reset, and Power Control7. P
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Chapter 11Design for TestThis chapt
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Design for Test11.1.2 MBIST registe
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Design for Testdseed[3:0]Write the
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Design for TestNoteOnly arrays with
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Design for Test• read and write l
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Design for TestTable 11-10 Selectin
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Design for TestTable 11-15 shows ho
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Design for TestArrayFail[22:0] fail
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Design for TestWhen testing the tag
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Design for Test• Bitmap test mode
- Page 403 and 404:
Design for TestCLKARESETnMBISTMODEM
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Design for TestCLKARESETnMBISTMODEM
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Design for TestTable 11-19 shows th
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Design for TestNoteNormal MBIST tes
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Design for TestRowmaxmax - 11 1 1 1
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Design for Test2. R, W_, R_, incr.3
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Design for TestRow3210Addressingdir
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Design for TestRow32100 00 00 00 00
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Design for Test11.2 ATPG test featu
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Design for TestWBR in place of the
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Design for TestOne methodology for
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Chapter 12DebugThis chapter describ
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Debug12.1.3 Debug targetThe debug t
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DebugWhen execution of a monitor ta
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Debug12.3 Debug register interfaceY
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DebugTable 12-3 Debug memory-mapped
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Debug12.3.6 Power domains and debug
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DebugLocks permissionYou can lock t
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DebugTable 12-6 shows the behavior
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Debug12.4 Debug register descriptio
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DebugTable 12-11 shows how the bit
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DebugThe Debug Self Address Offset
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DebugBits Field FunctionTable 12-14
- Page 449 and 450:
DebugBits Field FunctionTable 12-14
- Page 451 and 452:
DebugBits Field Function[9] - Reser
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DebugThe DTR access mode can be one
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DebugBitsFieldFunctionTable 12-16 s
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DebugTable 12-17 Vector Catch Regis
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Debug31 3 2 1 0ReservedNot write-th
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DebugBits Field FunctionTable 12-21
- Page 463 and 464:
DebugBits Field FunctionTable 12-23
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DebugTable 12-23 Breakpoint Control
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Debug12.4.16 Watchpoint Control Reg
- Page 469 and 470:
DebugTable 12-26 Watchpoint Control
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DebugBits Field FunctionTable 12-27
- Page 473 and 474:
DebugBits Field FunctionTable 12-29
- Page 475 and 476:
DebugBits Field FunctionTable 12-30
- Page 477 and 478:
DebugNoteOn system reset, PRSR[1] r
- Page 479 and 480:
DebugTable 12-32 Management registe
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DebugFigure 12-19 shows the bit arr
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DebugBits Field FunctionTable 12-35
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Debug12.5.5 Integration Mode Contro
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Debug12.5.8 Lock Access RegisterThe
- Page 489 and 490:
Debug31 8 7 6 5 4 3 2 1 0ReservedSe
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DebugTable 12-44 Peripheral Identif
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DebugTable 12-50 shows how the bit
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Debug12.6.2 Halting debug event•
- Page 497 and 498:
Debug12.6.5 Watchpoint debug events
- Page 499 and 500:
DebugNoteThe Data Abort handler che
- Page 501 and 502:
DebugIf the debugged code is not ru
- Page 503 and 504:
DebugTable 12-54 shows the read PC
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Debug12.8.4 Writing to the CPSR in
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DebugCoprocessor instructionsThe ru
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DebugSVCSMCUndefinedThe processor i
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Debug12.9 Cache debugThere are seve
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Debug12.10 External debug interface
- Page 515 and 516:
DebugDBGROMADDRThe DBGROMADDR signa
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Debug4. Issue an Instruction Synchr
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Debug12.11.1 Debug communications c
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DebugDebugger access to the DCCA de
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DebugTable 12-58 Values to write to
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Debug}when 1:byte_address_select :=
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DebugNoteIn Example 12-10 on page 1
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Debug12.11.5 Debug state exitWhen e
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DebugExample 12-15 Reading the PCRe
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DebugExample 12-19 Checking for an
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DebugExample 12-22 shows the sequen
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Debug}dscr := ReadDebugRegister(34)
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Debug}scr := (scr | 1);WriteCPReg(1
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DebugIf on a power-down request fro
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Debug; Step 2. Loop writing words f
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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NEON and VFP Programmer’s ModelS0
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NEON and VFP Programmer’s ModelBa
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NEON and VFP Programmer’s ModelFC
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NEON and VFP Programmer’s ModelTa
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NEON and VFP Programmer’s ModelTa
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NEON and VFP Programmer’s Model31
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NEON and VFP Programmer’s ModelTh
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NEON and VFP Programmer’s ModelTa
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NEON and VFP Programmer’s Model13
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NEON and VFP Programmer’s Model13
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NEON and VFP Programmer’s ModelCo
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Chapter 14Embedded Trace MacrocellT
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Embedded Trace Macrocell14.1.2 The
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Embedded Trace Macrocell(DAP) throu
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Embedded Trace MacrocellTable 14-1
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Embedded Trace MacrocellRegister na
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Embedded Trace MacrocellTable 14-3
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Embedded Trace MacrocellTable 14-4
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Embedded Trace MacrocellTable 14-6
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Embedded Trace MacrocellSee the ETM
- Page 589 and 590:
Embedded Trace MacrocellTable 14-11
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Embedded Trace MacrocellTable 14-14
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Embedded Trace Macrocell14.5 Precis
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Embedded Trace MacrocellThe followi
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Embedded Trace Macrocellcomparator
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Embedded Trace Macrocell14.8 Instru
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Embedded Trace MacrocellWhen a WFI
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Embedded Trace MacrocellTable 14-17
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Embedded Trace MacrocellYou can use
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Chapter 15Cross Trigger InterfaceTh
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Cross Trigger Interface• An input
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Cross Trigger Interface15.1.2 The c
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Cross Trigger InterfaceTable 15-2 T
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Cross Trigger Interface15.4 About t
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Cross Trigger InterfaceTable 15-3 C
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Cross Trigger Interface15.6 CTI reg
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Cross Trigger InterfaceNoteThe CTII
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Cross Trigger InterfaceBits Field F
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Cross Trigger Interface15.6.9 CTI T
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Cross Trigger InterfaceTable 15-14
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Cross Trigger InterfaceTable 15-16
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Cross Trigger InterfaceTable 15-18
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Cross Trigger Interface15.7.4 ITTRI
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Cross Trigger InterfaceTable 15-26
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Cross Trigger Interface15.8.3 Devic
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Cross Trigger InterfaceActual Compo
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Chapter 16Instruction Cycle TimingT
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Instruction Cycle Timing16.2 Instru
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Instruction Cycle Timingis availabl
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Instruction Cycle TimingTable 16-4
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Instruction Cycle Timing16.2.7 Stat
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Instruction Cycle TimingThe number
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Instruction Cycle Timing16.3 Dual-i
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Instruction Cycle TimingReplayevent
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Instruction Cycle TimingPredicting
- Page 659 and 660:
Instruction Cycle TimingUsing MCR i
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Instruction Cycle TimingExample 16-
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Instruction Cycle TimingTable 16-15
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Instruction Cycle Timing16.6.3 Adva
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Instruction Cycle TimingTable 16-16
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Instruction Cycle Timing16.6.5 Adva
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Instruction Cycle TimingTable 16-19
- Page 673 and 674:
Instruction Cycle TimingFor example
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Instruction Cycle TimingTable 16-20
- Page 677 and 678:
Instruction Cycle TimingTable 16-20
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Instruction Cycle TimingTable 16-20
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Instruction Cycle Timing16.7 VFP in
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Instruction Cycle TimingTable 16-22
- Page 685 and 686:
Instruction Cycle Timing16.7.2 VFP
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Chapter 17AC CharacteristicsThis ch
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AC CharacteristicsThe timing parame
- Page 691 and 692:
AC CharacteristicsTable 17-2 Timing
- Page 693 and 694:
AC Characteristics17.4 APB interfac
- Page 695 and 696:
AC Characteristics17.5 L1 and L2 MB
- Page 697 and 698:
AC Characteristics17.7 DFT interfac
- Page 699 and 700:
AC Characteristicsb. Figure 10-6 on
- Page 701 and 702:
Appendix ASignal DescriptionsThis a
- Page 703 and 704:
Signal DescriptionsA.2 ATB interfac
- Page 705 and 706:
Signal DescriptionsTable A-3 MBIST
- Page 707 and 708:
Signal DescriptionsA.4 Preload engi
- Page 709 and 710:
Signal DescriptionsTable A-6 APB in
- Page 711 and 712:
Signal DescriptionsTable A-7 Miscel
- Page 713 and 714:
Signal DescriptionsTable A-7 Miscel
- Page 715 and 716:
Signal DescriptionsTable A-8 Miscel
- Page 717 and 718:
Signal DescriptionsA.8 Miscellaneou
- Page 719 and 720:
Appendix BInstruction MnemonicsThis
- Page 721 and 722:
Instruction MnemonicsTable B-1 Adva
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Instruction MnemonicsB.2 VFP data-p
- Page 725 and 726:
GlossaryThis glossary describes som
- Page 727 and 728:
GlossaryApplication Specific Integr
- Page 729 and 730:
GlossaryRead ID capabilityThe maxim
- Page 731 and 732:
GlossaryByte-invariantIn a byte-inv
- Page 733 and 734:
GlossaryCAM includes comparison log
- Page 735 and 736:
GlossaryDouble-precision valueConsi
- Page 737 and 738:
Glossary• arithmetic operation re
- Page 739 and 740:
GlossaryInvalidateJazelle architect
- Page 741 and 742:
GlossaryPAPenaltyPower-on resetPref
- Page 743 and 744:
GlossarySetSet-associative cacheSee
- Page 745 and 746:
GlossaryTrapTrigger instructionAn e
- Page 747 and 748:
GlossaryWrite-back (WB)Write buffer