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Introduction1.3.4 Load/storeThe load/store unit encompasses the entire L1 data side memory system and the integerload/store pipeline. This includes:• the L1 data cache• the data side TLB• the integer store buffer• the NEON store buffer• the integer load data alignment and formatting• the integer store data alignment and formatting.The pipeline accepts one load or store per cycle that can be present in either pipeline 0or pipeline 1. This gives the processor flexibility when scheduling load and storeinstructions. See Chapter 7 Level 1 Memory System for more information.1.3.5 L2 cacheThe L2 cache unit includes the L2 cache and the Buffer Interface Unit (BIU). It servicesL1 cache misses from both the instruction fetch unit and the load/store unit. SeeChapter 8 Level 2 Memory System and Chapter 9 External Memory Interface for moreinformation.1.3.6 NEONThe NEON unit includes the full 10-stage NEON pipeline that decodes and executes theAdvanced SIMD media instruction set. The NEON unit includes:• the NEON instruction queue• the NEON load data queue• two pipelines of NEON decode logic• three execution pipelines for Advanced SIMD integer instructions• two execution pipelines for Advanced SIMD floating-point instructions• one execution pipeline for Advanced SIMD and VFP load/store instructions• the VFP engine for full execution of the VFPv3 data-processing instruction set.See Chapter 13 NEON and VFP Programmer’s Model for programming information onthe NEON and VFP coprocessor.1.3.7 ETMThe ETM unit is a non-intrusive trace macrocell that filters and compresses aninstruction and data trace for use in system debugging and system profiling.1-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
IntroductionThe ETM unit has an external interface outside of the processor called the AdvancedTrace Bus (ATB) interface. See Chapter 14 Embedded Trace Macrocell for moreinformation.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 1-7
Page 1 and 2: Cortex -A8Revision: r2p2Technical R
Page 3 and 4: Product StatusThe information in th
Page 5 and 6: ContentsCortex-A8 Technical Referen
Page 7 and 8: Contents7.8 Parity detection ......
Page 9 and 10: ContentsA.2 ATB interface .........
Page 11 and 12: List of TablesCortex-A8 Technical R
Page 14 and 15: List of TablesTable 3-103 Results o
Page 16 and 17: List of TablesTable 12-1 Access to
Page 18 and 19: List of TablesTable 15-3 CTI regist
Page 20 and 21: List of Tablesxx Copyright © 2006-
Page 22 and 23: List of FiguresFigure 3-10 Memory M
Page 24 and 25: List of FiguresFigure 10-13 Retenti
Page 26 and 27: List of FiguresFigure 15-16 CTI Cha
Page 28 and 29: PrefaceAbout this manualThis is the
Page 30 and 31: PrefaceChapter 16 Instruction Cycle
Page 32 and 33: PrefacePrefix CPrefix HPrefix nPref
Page 34 and 35: PrefaceFeedbackARM welcomes feedbac
Page 36 and 37: Introduction1.1 About the processor
Page 38 and 39: Introduction1.3 Components of the p
Page 42 and 43: Introduction1.4 External interfaces
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Page 50 and 51: Programmer’s Model• Hardware co
Page 52 and 53: Programmer’s Model2.2 Thumb-2 ins
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control Coprocessora. An ent
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System Control CoprocessorThe Auxil
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System Control CoprocessorBits Fiel
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System Control Coprocessora. n is t
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System Control CoprocessorInvalidat
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System Control CoprocessorThe PMNC
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System Control Coprocessorb. The EN
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorIf the op
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System Control CoprocessorTo access
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System Control Coprocessora. An ent
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
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System Control CoprocessorTo perfor
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System Control CoprocessorLDR R1, =
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
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System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
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Chapter 4Unaligned Data and Mixed-e
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Unaligned Data and Mixed-endian Dat
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Unaligned Data and Mixed-endian Dat
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Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
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Program Flow Prediction5.2.1 Return
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Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
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Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
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Level 1 Memory System7.2 Cache orga
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Level 1 Memory System7.3 Memory att
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Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
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Level 1 Memory SystemAn exception t
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Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
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Level 2 Memory System8.2 Cache orga
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Level 2 Memory System8.3 Enabling a
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Level 2 Memory SystemControl Regist
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Level 2 Memory System8.4.4 Memory r
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Level 2 Memory System8.5 Synchroniz
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Chapter 9External Memory InterfaceT
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External Memory Interfaceto the wri
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External Memory InterfaceTable 9-2
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External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
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Chapter 10Clock, Reset, and Power C
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Clock, Reset, and Power Controlfami
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Clock, Reset, and Power Control10.2
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control2. F
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Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlThe
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlTo p
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Clock, Reset, and Power ControlATBI
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Clock, Reset, and Power Control7. P
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Chapter 11Design for TestThis chapt
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Design for Test11.1.2 MBIST registe
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Design for Testdseed[3:0]Write the
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Design for TestNoteOnly arrays with
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Design for Test• read and write l
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Design for TestTable 11-10 Selectin
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Design for TestTable 11-15 shows ho
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Design for TestArrayFail[22:0] fail
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Design for TestWhen testing the tag
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Design for Test• Bitmap test mode
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Design for TestCLKARESETnMBISTMODEM
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Design for TestTable 11-19 shows th
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Design for TestNoteNormal MBIST tes
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Design for TestRowmaxmax - 11 1 1 1
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Design for Test2. R, W_, R_, incr.3
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Design for TestRow3210Addressingdir
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Design for TestRow32100 00 00 00 00
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Design for Test11.2 ATPG test featu
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Design for TestWBR in place of the
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Design for TestOne methodology for
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Chapter 12DebugThis chapter describ
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Debug12.1.3 Debug targetThe debug t
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DebugWhen execution of a monitor ta
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Debug12.3 Debug register interfaceY
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DebugTable 12-3 Debug memory-mapped
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Debug12.3.6 Power domains and debug
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DebugLocks permissionYou can lock t
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DebugTable 12-6 shows the behavior
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Debug12.4 Debug register descriptio
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DebugTable 12-11 shows how the bit
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DebugThe Debug Self Address Offset
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DebugBits Field FunctionTable 12-14
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DebugBits Field Function[9] - Reser
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DebugThe DTR access mode can be one
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DebugBitsFieldFunctionTable 12-16 s
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DebugTable 12-17 Vector Catch Regis
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Debug31 3 2 1 0ReservedNot write-th
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DebugTable 12-23 Breakpoint Control
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Debug12.4.16 Watchpoint Control Reg
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DebugNoteOn system reset, PRSR[1] r
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DebugTable 12-32 Management registe
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Debug12.5.5 Integration Mode Contro
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Debug31 8 7 6 5 4 3 2 1 0ReservedSe
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DebugTable 12-44 Peripheral Identif
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DebugTable 12-50 shows how the bit
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Debug12.6.2 Halting debug event•
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Debug12.6.5 Watchpoint debug events
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DebugNoteThe Data Abort handler che
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DebugIf the debugged code is not ru
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DebugTable 12-54 shows the read PC
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Debug12.8.4 Writing to the CPSR in
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DebugCoprocessor instructionsThe ru
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Debug12.9 Cache debugThere are seve
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DebugDBGROMADDRThe DBGROMADDR signa
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Debug4. Issue an Instruction Synchr
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Debug12.11.1 Debug communications c
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DebugDebugger access to the DCCA de
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DebugTable 12-58 Values to write to
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Debug}when 1:byte_address_select :=
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Debug12.11.5 Debug state exitWhen e
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DebugExample 12-15 Reading the PCRe
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Debug}dscr := ReadDebugRegister(34)
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DebugIf on a power-down request fro
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Debug; Step 2. Loop writing words f
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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Chapter 14Embedded Trace MacrocellT
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Embedded Trace Macrocell14.1.2 The
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Embedded Trace Macrocell(DAP) throu
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Embedded Trace MacrocellTable 14-1
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Embedded Trace MacrocellSee the ETM
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Embedded Trace MacrocellThe followi
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Embedded Trace Macrocellcomparator
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Embedded Trace Macrocell14.8 Instru
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Embedded Trace MacrocellWhen a WFI
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Embedded Trace MacrocellYou can use
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Chapter 15Cross Trigger InterfaceTh
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Cross Trigger Interface• An input
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Cross Trigger Interface15.1.2 The c
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Cross Trigger InterfaceTable 15-2 T
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Cross Trigger Interface15.4 About t
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Cross Trigger InterfaceTable 15-3 C
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Cross Trigger InterfaceTable 15-14
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Cross Trigger InterfaceActual Compo
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Chapter 16Instruction Cycle TimingT
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Instruction Cycle Timing16.2 Instru
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Instruction Cycle TimingTable 16-4
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Instruction Cycle Timing16.2.7 Stat
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Instruction Cycle Timing16.3 Dual-i
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Instruction Cycle TimingReplayevent
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Instruction Cycle TimingExample 16-
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Chapter 17AC CharacteristicsThis ch
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AC CharacteristicsThe timing parame
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AC CharacteristicsTable 17-2 Timing
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AC Characteristics17.4 APB interfac
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AC Characteristics17.5 L1 and L2 MB
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AC Characteristics17.7 DFT interfac
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AC Characteristicsb. Figure 10-6 on
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Appendix ASignal DescriptionsThis a
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Signal DescriptionsA.2 ATB interfac
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Signal DescriptionsTable A-3 MBIST
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Signal DescriptionsA.4 Preload engi
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Signal DescriptionsTable A-7 Miscel
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Signal DescriptionsA.8 Miscellaneou
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Appendix BInstruction MnemonicsThis
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Instruction MnemonicsTable B-1 Adva
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Instruction MnemonicsB.2 VFP data-p
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GlossaryThis glossary describes som
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GlossaryApplication Specific Integr
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GlossaryRead ID capabilityThe maxim
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GlossaryByte-invariantIn a byte-inv
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GlossaryCAM includes comparison log
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GlossaryDouble-precision valueConsi
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Glossary• arithmetic operation re
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GlossaryInvalidateJazelle architect
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GlossaryPAPenaltyPower-on resetPref
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GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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