Cortex-A8 R2P2.pdf - ARM Information Center

List of FiguresFigure 3-57 PLE Internal Start Address Register bit format ..................................................... 3-147Figure 3-58 PLE Internal End Address Register format ........................................................... 3-148Figure 3-59 PLE Channel Status Register format .................................................................... 3-150Figure 3-60 PLE Context ID Register format ............................................................................ 3-152Figure 3-61 Secure or Nonsecure Vector Base Address Register format ................................ 3-154Figure 3-62 Monitor Vector Base Address Register format ...................................................... 3-155Figure 3-63 Interrupt Status Register format ............................................................................ 3-157Figure 3-64 FCSE PID Register format .................................................................................... 3-159Figure 3-65 Address mapping with the FCSE PID Register ..................................................... 3-160Figure 3-66 Context ID Register format .................................................................................... 3-161Figure 3-67 Instruction and Data side Data 0 Registers format ............................................... 3-164Figure 3-68 Instruction and Data side Data 1 Registers format ............................................... 3-165Figure 3-69 L1 TLB CAM read operation format ...................................................................... 3-169Figure 3-70 L1 TLB CAM write operation format ...................................................................... 3-169Figure 3-71 L1 HVAB array read operation format ................................................................... 3-172Figure 3-72 L1 HVAB array write operation format .................................................................. 3-172Figure 3-73 L1 tag array read operation format ........................................................................ 3-173Figure 3-74 L1 tag array write operation format ....................................................................... 3-173Figure 3-75 L1 data array read operation format ...................................................................... 3-174Figure 3-76 L1 data array write operation format ..................................................................... 3-175Figure 3-77 BTB array read operation format ........................................................................... 3-176Figure 3-78 BTB array write operation format .......................................................................... 3-177Figure 3-79 GHB array read operation format .......................................................................... 3-178Figure 3-80 GHB array write operation format ......................................................................... 3-178Figure 3-81 L2 Data 0 Register format ..................................................................................... 3-179Figure 3-82 L2 Data 1 Register format ..................................................................................... 3-179Figure 3-83 L2 Data 2 Register format ..................................................................................... 3-180Figure 3-84 L2 parity/ECC array read operation format ........................................................... 3-182Figure 3-85 L2 parity/ECC array write operation format ........................................................... 3-183Figure 3-86 L2 tag array read operation format ........................................................................ 3-184Figure 3-87 L2 tag array write operation format ....................................................................... 3-184Figure 3-88 L2 data RAM array read operation format ............................................................. 3-185Figure 3-89 L2 data RAM array write operation format ............................................................ 3-185Figure 6-1 16MB supersection descriptor format ....................................................................... 6-4Figure 8-1 L2 cache bank structure ............................................................................................ 8-4Figure 10-1 CLK duty cycle ........................................................................................................ 10-2Figure 10-2 CLK-to-ACLK ratio of 4:1 ........................................................................................ 10-3Figure 10-3 Changing the CLK-to-ACLK ratio from 4:1 to 1:1 .................................................... 10-3Figure 10-4 Changing the PCLK-to-internal-PCLK ratio from 4:1 to 1:1 .................................... 10-4Figure 10-5 Changing the ATCLK-to-internal-ATCLK ratio from 4:1 to 1:1 ................................ 10-4Figure 10-6 Power-on reset timing ............................................................................................. 10-6Figure 10-7 Soft reset timing ...................................................................................................... 10-7Figure 10-8 PRESETn and ATRESETn assertion ...................................................................... 10-8Figure 10-9 STANDBYWFI deassertion ................................................................................... 10-11Figure 10-10 CLKSTOPREQ and CLKSTOPACK ..................................................................... 10-12Figure 10-11 Power domains ..................................................................................................... 10-16Figure 10-12 Voltage domains ................................................................................................... 10-18ARM DDI 0344E Copyright © 2006-2008 ARM Limited. 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