Cortex-A8 R2P2.pdf - ARM Information Center

List of TablesTable 12-48 Peripheral ID Register 2 bit functions .................................................................... 12-68Table 12-49 Peripheral ID Register 3 bit functions .................................................................... 12-68Table 12-50 Peripheral ID Register 4 bit functions .................................................................... 12-69Table 12-51 Component Identification Registers ...................................................................... 12-69Table 12-52 Processor behavior on debug events .................................................................... 12-72Table 12-53 Values in Link Register after exceptions ............................................................... 12-75Table 12-54 Read PC value after debug state entry ................................................................. 12-79Table 12-55 Permitted updates to the CPSR in debug state .................................................... 12-82Table 12-56 Accesses to CP15 and CP14 registers in debug state ......................................... 12-83Table 12-57 Authentication signal restrictions ........................................................................... 12-91Table 12-58 Values to write to BCR for a simple breakpoint ..................................................... 12-98Table 12-59 Values to write to WCR for a simple watchpoint ................................................. 12-100Table 12-60 Example byte address masks for watchpointed objects ..................................... 12-101Table 13-1 Single-precision three-operand register usage ..................................................... 13-10Table 13-2 Single-precision two-operand register usage ........................................................ 13-11Table 13-3 Double-precision three-operand register usage .................................................... 13-11Table 13-4 Double-precision two-operand register usage ...................................................... 13-11Table 13-5 NEON and VFP system registers .......................................................................... 13-12Table 13-6 Accessing NEON and VFP system registers ........................................................ 13-12Table 13-7 FPSID Register bit functions ................................................................................. 13-14Table 13-8 FPSCR Register bit functions ............................................................................... 13-15Table 13-9 Vector length and stride combinations .................................................................. 13-17Table 13-10 Floating-Point Exception Register bit functions ..................................................... 13-18Table 13-11 MVFR0 Register bit functions ............................................................................... 13-19Table 13-12 MVFR1 Register bit functions ............................................................................... 13-20Table 13-13 Default NaN values ............................................................................................... 13-23Table 13-14 QNaN and SNaN handling .................................................................................... 13-24Table 14-1 ETM implementation ............................................................................................... 14-6Table 14-2 ETM register summary ............................................................................................ 14-8Table 14-3 ID Register bit functions ........................................................................................ 14-11Table 14-4 Configuration Code Register bit functions ............................................................. 14-12Table 14-5 Configuration Code Extension Register bit functions ............................................ 14-13Table 14-6 Peripheral Identification Registers bit functions .................................................... 14-14Table 14-7 Component Identification Registers bit functions .................................................. 14-16Table 14-8 Output signals that can be controlled by the Integration Test Registers ............... 14-17Table 14-9 Input signals that can be read by the Integration Test Registers .......................... 14-17Table 14-10 ITMISCOUT Register bit functions ........................................................................ 14-18Table 14-11 ITMISCIN Register bit functions ............................................................................ 14-19Table 14-12 ITTRIGGER Register bit functions ........................................................................ 14-19Table 14-13 ITATBDATA0 Register bit functions ...................................................................... 14-20Table 14-14 ITATBCTR2 Register bit functions ........................................................................ 14-21Table 14-15 ITATBCTR1 Register bit functions ........................................................................ 14-21Table 14-16 ITATBCTR0 Register bit functions ........................................................................ 14-22Table 14-17 PMU event number mappings ............................................................................... 14-32Table 14-18 PMU event cycle mappings ................................................................................... 14-34Table 15-1 Trigger inputs .......................................................................................................... 15-6Table 15-2 Trigger outputs ........................................................................................................ 15-6ARM DDI 0344E Copyright © 2006-2008 ARM Limited. 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