Cortex-A8 R2P2.pdf - ARM Information Center

List of TablesTable 3-9 TLB Type Register bit functions .............................................................................. 3-29Table 3-10 Results of access to the TLB Type Register ........................................................... 3-29Table 3-11 Results of access to the Multiprocessor ID Register .............................................. 3-30Table 3-12 Processor Feature Register 0 bit functions ............................................................. 3-31Table 3-13 Results of access to the Processor Feature Register 0 .......................................... 3-31Table 3-14 Processor Feature Register 1 bit functions ............................................................. 3-32Table 3-15 Results of access to Processor Feature Register 1 ................................................ 3-32Table 3-16 Debug Feature Register 0 bit functions .................................................................. 3-33Table 3-17 Results of access to Debug Feature Register 0 ..................................................... 3-34Table 3-18 Results of access to Auxiliary Feature Register 0 .................................................. 3-35Table 3-19 Memory Model Feature Register 0 bit functions ..................................................... 3-36Table 3-20 Results of access to Memory Model Feature Register 0 ........................................ 3-36Table 3-21 Memory Model Feature Register 1 bit functions ..................................................... 3-37Table 3-22 Results of access to Memory Model Feature Register 1 ........................................ 3-39Table 3-23 Memory Model Feature Register 2 bit functions ..................................................... 3-40Table 3-24 Results of access to Memory Model Feature Register 2 ........................................ 3-41Table 3-25 Memory Model Feature Register 3 bit functions ..................................................... 3-42Table 3-26 Results of access to Memory Model Feature Register 3 ........................................ 3-42Table 3-27 Instruction Set Attributes Register 0 bit functions ................................................... 3-43Table 3-28 Results of access to Instruction Set Attributes Register 0 ...................................... 3-44Table 3-29 Instruction Set Attributes Register 1 bit functions ................................................... 3-45Table 3-30 Results of access to Instruction Set Attributes Register 1 ...................................... 3-46Table 3-31 Instruction Set Attributes Register 2 bit functions ................................................... 3-47Table 3-32 Results of access to Instruction Set Attributes Register 2 ...................................... 3-48Table 3-33 Instruction Set Attributes Register 3 bit functions ................................................... 3-49Table 3-34 Results of access to Instruction Set Attributes Register 3 ...................................... 3-50Table 3-35 Instruction Set Attributes Register 4 bit functions ................................................... 3-51Table 3-36 Results of access to Instruction Set Attributes Register 4 ...................................... 3-51Table 3-37 Cache Level ID Register bit functions ..................................................................... 3-52Table 3-38 Results of access to the Cache Level ID Register .................................................. 3-53Table 3-39 Silicon ID Register bit functions .............................................................................. 3-54Table 3-40 Results of access to the Silicon ID Register ........................................................... 3-54Table 3-41 Cache Size Identification Register bit functions ...................................................... 3-55Table 3-42 Encodings of the Cache Size Identification Register .............................................. 3-56Table 3-43 Results of access to the Cache Size Identification Register ................................... 3-56Table 3-44 Cache Size Selection Register bit functions ........................................................... 3-57Table 3-45 Results of access to the Cache Size Selection Register ........................................ 3-57Table 3-46 Control Register bit functions .................................................................................. 3-59Table 3-47 Results of access to the Control Register ............................................................... 3-61Table 3-48 Behavior of the processor when enabling caches .................................................. 3-61Table 3-49 Auxiliary Control Register bit functions ................................................................... 3-63Table 3-50 Results of access to the Auxiliary Control Register ................................................ 3-66Table 3-51 Coprocessor Access Control Register bit functions ................................................ 3-67Table 3-52 Results of access to the Coprocessor Access Control Register ............................. 3-68Table 3-53 Secure Configuration Register bit functions ........................................................... 3-70Table 3-54 Operation of the FW and FIQ bits ........................................................................... 3-71Table 3-55 Operation of the AW and EA bits ............................................................................ 3-71xii Copyright © 2006-2008 ARM Limited. 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