ishigaki presen.pdf

Doctor ThesisA Study on Silicon-on-Thin-BOX (SOTB)CMOSFET for Low-Power LSIsTakashi IshigakiSupervisor: Prof. Iwai and Prof. Sugii

Outline21. Biography2. Introduction3. Purpose of this study4. Chapter 2~65. Conclusion6. Publications

Power Dissipation in Japan (BkWh)2. Introduction• In 2025, five times larger power consumption is expected inJapan than that in 2005. Low power IT is urgently desired.2520(((Source: 出 展 ) 経 済 Ministry 産 業 省 /グリーンIT of Economy, 推 進 協 Trade 議 会 試 and 算 (2008) Industry (METI))Network(router, switch)151050TV2005 2010 2015 2020 2025(Year)PCServer4

CO 2 emissionSustainable and Innovative Society• Green IT & LSI technology can attribute much tosustainable society.1992 2002 2005Red area shows ice melted in that yearGreenland ice-melt(estimates sea level rise to six meterswhen melted all)Source: Al Gore, An Inconvenient TruthConventional trendLower Power by InnovationNew: Normally-OFF, Instant-ONwith conventional nano Tr.,low-voltage, multi-core, etc.Direction forsustainable andinnovative societyTarget as carbonemission in 2007G8 Summit@HeiligendammGermany 2007.619902005 2025 2050(year)5

Power consumption of LSI6• Lower supply voltage V dd is essential.P = n (CV dd2 f + I leak V dd )AC powerleakagen: number of transistorsC: load capacitanceV dd : supply voltagef: frequencyI leak : leakage currentLow-power technologies1) AC power2) leakage3) total power⇒⇒⇒reduce V dd , f, or Creduce I leak or V ddreduce n (i.e., power SW, clock gating...)

V dd (V)V dd forecast, past and present7• V dd is stagnated around 1 V due to V th variation issue.3.53.02.52.01.51.00.5NTRS (SIA)1-V brickwallITRS 2007-20110.01995 2000 2005 2010 2015 2020YearNTRS1994NTRS1997ITRS2007 (HP)ITRS2007 (LSTP)ITRS2011 (HP)ITRS2011 (LSTP)Variabilityissue

NumbersV th (arb. unit)Increasing V th variationClassificationwafer to wafer(process)die to die(process)cool but slow…fast but hotIntra-die(dopant)Increasing V th variationsV th (Total)sV th (Global)sV th (Local)V th130nm 90nm 65nm 45nm 32nmM. Yamaoka et al.,VLSI Circ., p.288, (2004)• Circuit stability limits V dd (especially in SRAM).• Small number of leaky (low V th ) transistorsincrease leakage of a chip.8

A Vt(mVm), t ox(nm)V th -variation scaling; current issue9A Vt decreased with scaling, however, slope issmaller than that of t ox . Why?100101642642A Vt :slope=0.72t ox : slope=1.06 80.12 4 6 812 4L min(m)K. Blut, ESSCIRC 2000, p. 126.Ideal scaling (constant electric field)L, W, t ox : 1/kN A (impurity): k (=√2)sV th t ox N A1/4/√LW k 1/4 =1.09The variation virtually increases byabout 9% per generation!(assuming impurity fluctuationdominant)Increasing V th variation is inherent problem with scaling.

Solution to reduce V th variationI d (A/µm)10Random dopant fluctuationV th and I off variationV bg 0worst I offGIDLUniformchannel profileIssuesRetrogradechannel profileA. Asenov et al., IEEE T-ED vol.48, p.772, vol.46, p.1722.Intra-die variation (dopant)Inter-die variation (process)V g(V)SolutionsLow-dose channelBack-gate-bias control

Intrinsic-channel structures: history11Fukuma et al., VLSI 1988 Aoki et al., IEDM 1990Yoshimi et al., TED 1989

Silicon-on-Thin-BOX (SOTB)• Realization in advanced generation isnecessary.Back-gate(V b )SOTB CMOSSTISOI ~12 nm(N SOI

Previous WorksGateRaised S/DL g (nm)SOI (nm)BOX (nm)I on (A/m)I off (nA/m)VariabilityBack-biasingRef.Poly-SiYes202020830/500100Not reportedNot reported[1.19]Poly-SiYes30105-25->1000Not reportedNot reported[1.20]Poly-SiYes701420480/680100Not reportedNot reported[1.21]Poly-Si gate devices with a lightly doped channelcannot be used for LSTP applications (I off ~ 0.02 nA/m).13

3. Purpose of this studySubjects of conventional devices:Bulk: V dd reduction, SCE, V th variationFDSOI: Low I on (R sd ), V th control, I/O device, Back-gating, Reliablity• To realize high-performance, low-power, reliable,and user-friendly SOTB CMOSFETSubjects Targets ApproachesRealizing SOTB CMOSFETin 65-nm generation・L g = 50 nm・Desirable and multi V th for LSTP・Comparable I on /I off・Less V th variation・Characterization of back-biasing・Combine FUSI gate and high raised S/D・Adjust the dopant concentration of thesubstrate beneath the BOX・Suppress SCE and RDF by FD-SOI structurewith low-dose channel・Propose a way of back-biasingReduction of powerconsumption・Ultralow off-current・Comparable inverter delay・Reduction of standby power・Reduction of V dd in SRAM・GIDL reduction by controlling L ov・Boosted performance in the case of ultralow I off・Ultralow I off and low variabilityCMOSFETs for I/O operation・Comparable characteristics toconventional bulk I/O CMOSFETs・Hybrid integration・Investigate the quality of the exposed surfaceHCI and NBTI reliability・Comparable lifetime to conventionalbulk CMOSFETs・Clarify the mechanism・Analsis of the electric fields in SOTBby using 2D simulator・Investigate the influence of back-biasingMIPS gate for SOTB・Desirable V th for LSTP・Non-degraded narrow channelcharacteristics・SiON/TiN/poly-Si gate・Less silicidation process14

Configuration of this thesisFor utilizationChapter 1IntroductionChapter 2Realization and Characterization ofSOTB CMOSFET in 65-nm GenerationFor high-performanceand low-powerChapter 4Hybrid Integration ofSOTB and Bulk CMOSFETsChapter 5HCI and NBTI Reliability ofSOTB CMOSFETChapter 3Reduction ofPower Consumptionby SOTB TechnologyChapter 6MIPS Gate Structure forSOTB CMOSFETChapter 7Conclusions15

17・Gate formationRaised S/D & FUSI-gate ProcessTEOS 50nmPoly Si 40nm・HTO depo.・SiN depo. & etch backSiN offsetspacer・Ion imp. for extentionSOI 15~20nm・SiN depo. & etch back・ pre-cleaning・SEG・Ion imp. for S/D・FUSINiSiNiSiNiSi50 nm

Drain current I d (A/m)Output characteristics19Self-heating free due to thin BOX600PMOSNMOS500L g = 50 nm400V g = 1.2 V300V g = -1.2 V1.0200- 1.00.8100- 0.8- 0.60.60-1.2 -0.8 -0.4 0 0.4 0.8 1.2Drain voltage V d (V)

SCE control and dual V th designV th (V)DIBL (mV/V)S (mV/dec.)0.80.6NMOSHigh V th : N back gate = 1 10 18 cm -30.40.2150Low V th : N back gate = 110 16 cm -3 201005001009080706040 50 60 70 100200Gate length L g (nm)

SCE control and dual V th designV th (V)DIBL (mV/V)S (mV/dec.)0-0.2PMOSLow V th : N back gate = 1 10 16 cm -3-0.4-0.615010050010090807060High V th : 1 10 18 cm -3 2140 50 60 70 100200Gate length L g (nm)

I off (A/m)I on -I off characteristicsI off (A/m)Superior characteristics to bulk CMOSFETs for LSTP.(I on = 550/320 A/m @ I off = 20 pA/m)10 -410 -510 -610 -710 -810 -910 -1010 -1110 -1210 -13I on = 550 A/mNMOSBulk Si(L poly 50~55 nm)I off = 20 pA/m0 200 400 600 800 1000I on (A/m)10 -410 -510 -610 -710 -810 -910 -1010 -1110 -1210 -13I on = 320 A/mPMOSBulk Si(L poly 50~55 nm)I off = 20 pA/m0 100 200 300 400 500I on (A/m)K. Kimizuka et al., VLSI Tech., p.218, (2005)K. Utsumi et al., VLSI Tech., p.216, (2005)Z. Luo et al., IEDM., p.661, (2004)22

|V th | (V)S (mV/dec.)Back-gate bias control in SOTB23Wide range V th controllability by back-gate bias.0.80.60.4 NMOSPMOS0.2L g = 50 nm100 0908070 NMOSPMOS60-1.5 -1 -0.5 0 0.5 1 1.5Back-gate bias V bg (V)

Suppression of global V th variationCumulative probability (%)24• Low variability and back-bias control were demonstrated.Adjusting V bg for each transistor (or chip)(“rough” 0.2 V step control; -1.2 V V bg 1.2 V)10080w/ V bg control(sV th < 8mV)60180 mV4020Cw/o V bg Control(sV th = 27mV)ABNMOSPoly-Si gateL poly = 45 nmV d = 1.2 V00 0.1 0.2 0.3V th (V)

V bg Dependence of V th Variation25Half sV th of conventional bulk CMOS under wide-range V bg .Normarized sV th2.521.510.5NMOSL g = 50 nmImprovedS-factorSOTBLSTP bulkEnhanced shortchannel effect0-1.5 -1 -0.5 0 0.5 1 1.5Back-gate bias V bg (V)

Conclusion of Chapter 226Simple FUSI gate process with high raised S/Dhas been developed for fabricating 65-nmSOTB.The suppressed SCE, superior I on /I off ,V th for LSTP & Dual V th , and half V th variationwere achieved.Wide-range back-bias control wasdemonstrated and its performance controlwas proposed for the first time.

Chapter 3Reduction of Power Consumptionby Using SOTB TechnologyPurpose of this chapterTo show what extent the power consumption can be reduced byusing SOTB (low variability, wide-range back-biasing, etc.)Subjects & TargetsApproaches1. Ultralow off-current2. Comparable t pd3. Reduction of standby power4. Reduction of V dd• GIDL reduction by controllingL ov• Boosted performance in thecase of ultralow off-current• Ultralow off-current & lowvariability: originarity in this thesis27

PerformanceCategory of Logic TransistorsFor further standby power reduction, GIDL must be reduced.ULSTP(Ultralow Standby Power)SOTB withforward-biasingHP(High Performance)LOP(Low Operation Power)LSTP(Low Standby Power)1 p 10 p 1 n 100 n(A/m)JL : Junction LeakageTransistor off-current I offJL GIDL Subthreshold leakageMajor causesof leakage28

GIDL (A/m)Device Design for GIDL ReductionI on / I on @L ov = 10 nm29Control of GIDL in SOTB is that only L ov need be considered.10 -3 110 -4 NMOSL ov10 -50.810 -6S G D10 -70.610 -8 I on10 -90.410 -10GIDL0.210 -11(I d @V g =-0.5V)10 -120-5 0 5 10Gate overlap lengh L ov (nm)

Drain current I d (A/m)• Off-current of 1 pA/m is achieved by reducing GIDL10 -3 Ultralow off-currentI off = 1 pA/m is achievedat I on = 313 (NMOS) / 232 (PMOS) A/m.10 -410 -510 -610 -710 -810 -910 -1010 -1110 -12PMOSV d = -50 mVL g = 50 nmL ov = 1 nm|V d | = 1.2 VV d = 50 mV10 -13-1.2 -0.8 -0.4 0 0.4 0.8 1.2Gate voltage V g (V)NMOSI off = 1 pA/m30

I d (A/m)I d (A/m)31Compensation of Variation by V bgThe worst I off can be reduced to 1/10, and the worst I on canbe improved up to 25 % by back-gate bias trimming.10 -3with V500bg40 chips10 -5 controlwith V bg 400control10 -7w/o V bg worst I 300controlon10 -925%worst I off20010 -111/10 w/o V bgI off = 1 pA/mcontrol10010 -13 00 0.4 0.8 1.2 0 0.4 0.8 1.2Gate Voltage V g (V)

Delay time pd (ps)Ring Osillator32Faster inverter delay time than conv. LSTP bulk was obtained.403020SOTB(L ov = 1, 4 nm)Ring Osillator61 stagesLSTPbulk100SOTB(L ov = 9 nm)Boost mode0 0.1 0.2 0.3 0.4 0.5Through current I cc (mA)

Standby current of1M transistors SRAMStandby Power Estimation33Due to the ultralow I off and low V th variation,the standby power can be reduced to 7 %.1.00.80.60.40.20I off =I standby 3 I off + 2 I g+6sVI off = thP(V th ) x I off (V th )- 6sV thBulk10 pA/m49 %SOTB10 pA/m-0.4P (%)SOTBBulk-0.2 0 0.2 0.4V th (V)7 %SOTB1 pA/mI offGL6sV th

V out (V)Measured butterfly curves of SOTB SRAMSNM (V)Over 100mV static noise margins are obtainedeven at the supply voltage of 0.6V1.41.21.00.80.6SOTB SRAM0.40.30.20.40.20.00.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4V in (V)0.10.00.4SNM: 357 mV@V dd = 1.2 V142 mV@V dd = 0.6 V0.60.8V dd (V)1.01.2R. Tsuchiya et al., IEDM. (2009)34

Conclusion of Chapter 335Ultralow I off (1 pA/m) SOTB has beendeveloped due to the GIDL reduction bycontrolling L ov .Faster inverter delay than conv. bulk was alsoachieved in the case of ultralow off-current.The standby power of LSI can be reduced to7 % because of the ultralow Ioff and low V thvariation.V dd can be reduced from 1.1 to 0.6 V in SRAMoperation due to the low V th variation.

Chapter 4Hybrid Integration of SOTB and Bulk CMOSFETsPurpose of this chapterTo integrate I/O bulk CMOSinto SOTBPreviousworkSubjects & Targets1. Simple hybrid integration2. Comparable characteristics3. Qualify the exposed surfaceof Si substrateM. Yang et al., TED, 53, p.965, (2006)Approaches• Low step height betweenSOTB and bulk regions• Investigate the influence ofsacrificial oxidation: originarity in this thesis36

Hybrid SOTB/Bulk Integration• Simple integration process of I/O bulk has been developed.process flowHybridSTI formationLow-stepUltra-thin BOX height bulk regionSOISub.ResistSTIPhoto resist patterningSOI etchingPoly-SigateSOISTI100nmUltra-thinBOX(10nm)Si substrateBOX removalSOIPoly-Si depositionBulk regionEasy fabricationCompatible with current bulkCMOS design37

Hybrid bulk CMOSFETsI d (A/m)Comparable characteristics were obtained.Fabricated Hybrid bulkwith FUSI gatesNiSi360nm50nm10 -410 -6I d – V g characteristicsPMOS NMOS|V d | = 0.05, 3.3 V10 -2 V g (V)Target ResultsV dd (V) 3.3 3.3L g (nm) 390 360T ox (nm) 7.5 7.5I on (NMOS) (A/m) 530 513I on (PMOS) (A/m) 275 272I off (NMOS) (pA/m) 0.1 8.9I off (PMOS) (pA/m) 0.5 410 -810 -1010 -12NiSi gateL d = 0.4 m-3 -2 -1 0 1 2 338

D it (eV -1 cm -2 )Investigation of the exposed surface eff (cm 2 /Vs)39Comparable quality was confirmed.Interface trap densityMobility10 12 Ref.w/o sacrificialoxidation with 10 nmsacr. ox.600500400polyuniversalFUSIw/o sacr. ox.NMOS10 1110 10Poly-Si gateNiSi gatew/o sacr. ox.Hybrid bulk trs.(Bulk sub.)300200100polyuniversalFUSIPMOS00 0.2 0.4 0.6 0.8 1E eff (MV/cm)

Conclusion of Chapter 440I/O bulk CMOSFETs was successfullyintegrated into SOTB technology.The quality of the exposed surface wasconfirmed.Comparable characteristics were alsoobtained.This hybrid technology can bring no designchange and the same usability for designers.

Chapter 5HCI and NBTI Reliability of SOTB CMOSFETPurpose of this chapterTo investigate the HCI and NBTIwith considering the effects of back-biasingSubjects & Targets1. Clarify the mechanism2. Guarantee the reliability(lifetime)Approaches• Analysis of the electric-fieldsin SOTB by using 2D simulator• Investigate the influence ofback-biasing: originarity in this thesis41

Comparison of I d – V d characteristicsDrain current, I d (A/m)•Comarable driving performance due to the raised S/D•Neither kink nor self-heating due to UT-SOI & BOX•Lower (~1 V) drain breakdown voltage (non-destructive)2000L g /W g = 55 nm/8 m15001000SOTB2.4 V2.8 V2.0 V50001.6 V1.2 VV g = 0.8 VBulk0 1 2 3 4Drain voltage, V d (V)42

V thsat (V d = 1.2V) shift (V)Comparison of HCI degradationPower-law slopes are ~0.5 in both SOTB and bulk.⇒ same degradation mechanism10 0 BulkL g /W g = 55 nm/8 m10 -110 -2~t 0.57SOTB~t 0.4910 -310 -4V d = V g = 2.2 V, V b = 0 VTemp. = RT10 0 10 1 10 2 10 3 10 4Stress time, t (sec.)43

V g dependence of HCI degradationV thsat (mV), |I dsat | (%)The worst case degradation is V g = V d .⇒ interface trap generation due to CHE2520V d = 2.2 V, V b = 0 VStress time = 1700 sec.15V thsat10Bulk5SOTBI dsat00 0.5 1 1.5 2 2.5Gate voltage, V g (V)44

Time@I dsat /I dsat0 = 10% (sec.)HCI LifetimeSOTB has longer lifetime at the operating voltage, 1.2 V.⇒ Why?1.2 V10 810 710 610 510 410 310 210 110 010 9 10 yearsSOTBBulkV d = V g = V stressV b = 0 V0.3 0.4 0.5 0.6 0.7 0.8 0.91/V stress (1/V)45

2D device simulationNet doping (/cm3)46Potential distribution are compared between SOTB and bulk.SOTBV g = V d = 2.4 VBulk with haloChannel impurity distribution222120191817161514チャネル 不 純 物 横 方 向 プロファイルx coordinate (um)SOTBBulk

Electric field strength E x (MV/cm)Simulated E x along the channelNo halo device has lower E x at drain edge,especially at 1.2 V.1.510.5V d = V g = V stress , V b = 0 VV stress = 2.4 VSOTB13%w/ haloV stress = 1.2 V0SourceChannelx positionDrain47

V thsat shift (V)Back-gate influence on HCI48Power-law slope increases as V b decreases.⇒ electron trapping increase due to the enhanced E yHowever, the worst condition is V b = V stress due to large I d .V d = V g = 2.4 V10 -1V b = 2.4 V10 -2-0.6 V10 -31.2 V-1.2 V10 010 -4Stress time (sec.)0 V10 0 10 1 10 2 10 3 10 4

HCI lifetime under back-gate stressTime@I dsat /I dsat0 = 10% (sec.)Even under a forward V b condition, HCI lifetime > 10 years10 810 710 610 510 410 310 210 110 010 9 10 yearsV b = 0 VV b = V d (Fwd.)V d = V g = V stress0.3 0.4 0.5 0.6 0.7 0.8 0.91/V stress (1/V)FUSI- gateSOTB49

V thsat shift (V)Comparison of NBTI degradationPower-law slopes are ~0.3 ⇒ Reaction-diffusion modelNBTI degradation is enhanceddue to the halo and/or a high energy implant.10 010 -1L g /W g = 55 nm/8 mV g - V th = -2.0 V, V b = 0 VTemp. = 125℃10 -2Bulkw/ halo10 -310 -4Poly-Si gateSOTB10 0 10 1 10 2 10 3 10 4 10 5Stress time (sec.)w/o halo50

V thsat shift (V)Back-gate influence on NBTISmall impact of back-bias V b on NBTI degradation.⇒ the influence of V b on the electric field of the channelsurface is mostly blocked by an inversion layer.10 010 -1V g = -2.6 V▽V b = 2.6V (Rev.)FUSI gateSOTB10 -210 -3◇V b = 0 V△V b = -2.6V (Fwd.)10 -410 0 10 1 10 2 10 3 10 4 10 5Stress time (sec.)51

Back-bias influence in SOTB CMOSFETs52inversionlayerGS V stress (V) D0 (V)-+ V stress (V)BOXBack-bias V b (V)HCI・Carrier density and Ey(especially at the drain edge)are modulated by Vb.・No substrate carrier injectioninversionlayerGS V stress (V) D0 (V)+ + +0 (V)BOXBack-bias V b (V)depletionlayerNBTI・Influence of Vb on Si surfaceis blocked by an inversionlayer・No substrate carrier injection

Conclusion of Chapter 553HCI degradation is mainly caused by CHE andForward back-biasing slightly shorten thelifetime (even though, longer lifetime than conv.Bulk due to no halo implant).NBTI degradation can be explained byReaction-Diffusion model and is much smallerthan conv. Bulk due to no halo implant.Back-biasing has small impact on NBTIbecause the inversion layer shields the effect.

Chapter 6MIPS Gate Structure for SOTB CMOSFETPurpose of this chapterTo optimize MIPS gate structurewith considering the SOTB processesSubjects & Targets1. V th for LSTP2. Clarify the mechanism3. Non-degraded narrowchannel characteristicsApproaches• SiON/TiN/poly-Si gate stack• Investigate the effectiveworkfunction modulation• Less silicidation process: originarity in this thesis54

Drain current (A/m)(@V g = -1.2 V)Narrow channel effects in FUSI-gate device55• Silicidation occurs from the side of raised S/D.• Fully silicided SOI layer results in high S/D resistance.250200FUSI gate PMOSSOI+Si epiCESLNiSi150BOX150 nmSTI100STI500L g = 70 nm, V dd = 1.2 V0.1 1 10Gate width (m)GateDSviewcutNarrow channel characteristics of FUSI-SOTBA TEM image of S/D region

MIPS Gate Stack for SOTB56Conv. Poly-Sifor easy fabricationCap SiNReliable SiON (~2 nm)without high-k for LSTP targetThin TiN for eWF controllSOIBOXSi sub.

V fb shifts depend on TiN thicknessFlat band voltage (V)Equivalent oxide thickness (nm)57• NMOS capacitor is investigated.• V fb shifts to midgap with thicker TiN.0.0-0.1-0.2-0.3-0.4-0.5-0.6-0.7-0.8-0.9-1.0w/ 1050℃ spike annealVfbEOT0 5 10 15TiN thickness (nm)3.02.52.01.51.00.50.0

Flat band voltage (V)Equivalent oxide thickness (nm)V fb shifts depend on thermal load• NMOS capacitor is investigated.• V fb shifts away from midgap with thermal load.0.0-0.1-0.2-0.3-0.4-0.5-0.6-0.7-0.8-0.9w/ 1050℃ spike annealVfbEOT-1.00 1 2 3 4 5No anneal+ 200min. anneal700℃ 800℃ 900℃3.02.52.01.51.00.50.058

N and P concentrations (/cm 3 )Backside SIMS profileTi, Si and O intensities (counts/s)59• SiON/TiN(8nm)/Poly-Si gate stack with a spike annealling• Diffusion of P from poly-Si was observed.1.E+24SiON / TiN / Poly-Si (P)1.E+061.E+231.E+051.E+22NTi1.E+041.E+21OSi1.E+031.E+201.E+19P1.E+021.E+011.E+180 5 10 15 20Depth (nm)1.E+00

Ti, Si and Ointensities (counts/s)Vfb (V)Vfb (V)V fb vs. SIMS profilesP concentrations (/cm 3 )60• V fb shifts correspond to P concentration.0.0-0.1-0.2-0.3-0.4-0.5-0.6-0.70 1 2 3 4 51.E+06sample1.E+05OSi1.E+04Ti1.E+03P1.E+021.E+011.E+000 1 2 3 4 5sample2.0E+201.5E+201.0E+205.0E+190.0E+00

TiN-gate SOTB MOSFETDrain current (A/m)(@V g = -1.2 V)61• Improved narrow channel characteristics due to lesssilicidation20 nmPoly-SiTiN (8 nm)250200150TiN gate PMOSSi epiSOI(11~12 nm)BOX (10 nm)SubstrateTiN / Poly-Si gate PMOS(Before silicide)100500L g = 70 nm, V dd = 1.2 V0.1 1 10Gate width (m)

Conclusion of Chapter 662V fb shift toward the midgap direction wasfound along with the increase in the TiNthickness and decrease in the thermal load.Diffusion of P from poly-Si into the TiN/SiONinterface was confirmed. And over 15 nm ofTiN thickness is necessary for symmetrical V th .The TiN-gate SOTB has no I on degradation innarrow channel due to the less silicidation.

5. Conclusion63SOTB CMOSFET for 65-nm LSTP has been successfullydeveloped. It has been experimentally demonstrated thatSOTB has superior characteristics, comparable designcapability, and higher reliability in comparison with bulkCMOSFETs.Both operating voltage and standby power can besubstantially reduced due to the half V th variation andback-bias control of SOTB.

Remained subjects and Future view64The remained subjects would be large scale integrationand circuit techniques (including SPICE models).Studies for these are now carried on into LEAP.Though FinFET is starting to be adopted in 22-nm, theproblems such as multi V th and back-biasing capabilitiesremain very difficult.SOTB technology is suitable for low-power SoC becauseof its high compatibility with current bulk CMOS not onlyin the future generation but also in the currentgeneration.

Design Enviroment65• SOTB/bulk hybrid circuits can be designed through theconv. flow. Need slight modifications and SPICE model.

Standard Cell66

6. Publications & Presentations67【Publications】-SOTB-•T. Ishigaki et al., "Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integratedwith Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode,”JJAP Vol. 47, 2585-2588, 2008.•T. Ishigaki et al., "Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasingperformance booster," Solid-State Electronics Vol. 53, 717-722, 2009.•T. Ishigaki et al., “Effects of Device Structure and Back Biasing on HCI and NBTI in Silicon –on-Thin-BOX(SOTB) CMOSFET,” Transactions on Electron Devices, Vol. 58, 1197-1204, 2011.•T. Ishigaki et al., “Investigation and integration of SiON/TiN/Poly-Si gate stack in Silicon-on-Thin-BOX(SOTB) CMOSFET,” JJAP, Vol. 51, 076504, 2012.-others-•T. Ishigaki et al., “Analysis of subband structures and optical properties of periodic strained quantumwires by a finite element method,” JAP Vol. 91, 5815-5819, 2002.【Presentations】-SOTB-•T. Ishigaki et al., "Wide-Range Vth Controllable SOTB (Silicon on Thin BOX) Integrated with Bulk CMOSFeaturing Fully Silicided NiSi Gate Electrode," SSDM, 886-887, 2007.•T. Ishigaki et al., "Silicon on Thin BOX (SOTB) CMOS for Ultralow Standby Power with Forward-biasingPerformance Booster", ESSDERC, 198-201, 2008.•T. Ishigaki et al., "HCI and NBTI including the effect of back-biasing in thin-BOX FD-SOI CMOSFETs,"IRPS, 1049-1052, 2010.-others-•T. Ishigaki et al., “Multi-level cell spin transfer torque memory with series-stacked magneto-tunneljunctions,” VLSI Technology, 47-48, 2010. (SPRAM)