HX8347 - Adafruit
HX8347 - Adafruit HX8347 - Adafruit
HX8347-G(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver4.1.3.2 4-wire serial interfaceDATA SHEET Preliminary V014-pin serial case, data packet contains just transmission byte and control bit DNC istransferred by DNC pin. If DNC is low, the transmission byte is command byte. If DNC ishigh, the transmission byte is stored to index register or GRAM. The MSB is transmittedfirst. The serial interface is initialized when NCS is high. In this state, NWR_SCL clockpulse or SDA data have no effect. A falling edge on NCS enables the serial interfaceand indicates the start of data transmission.4-Wire Serial Peripheral Interface ProtocolDNCNCSNWR_SCLSDAD7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0CommandParameterNCS can be "H" betweenCommand and parameterFigure 4.29: Index register write timing in 4-wire serial bus system interface16-bit Data Transfer Timing Format in 4-wire Serial Bus Interface for GRAM write ( Index 17h= 05)SCLSDAR14R13 R12 R11 R10 G15 G14 G13 G12 G11 G10B14B13B12B11B1016-bitLook-Up Table for 65K data mapping (16-bit to 18 bit)GRAM18-bitR1 G1 B1 R2 G2 B218-bit Data Transfer Timing Format in 4-wire Serial Bus Interface for GRAM write ( Index 17h= 06)SCLSDAR15R14R13 R12 R11 R10G15 G14 G13 G12 G11 G10B15B14B13B12B11B10GRAM18-bitR1 G1 B1 R2 G2 B2 R3 G3 B3Figure 4.30: Data write timing in 4-wire serial bus system interfaceHimax ConfidentialFor Go-tek OnlyThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.48-October, 2009
HX8347-G(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver4.2 RGB InterfaceDATA SHEET Preliminary V01The HX8347-G uses RCM [1:0] =’10’ or ‘11’ Software setting to select RGBinterface. After Power on Sequence, the RGB interface is activated. When RCM [1:0]=’10’ use VSYNC, HSYNC, DE, DOTCLK, DB17-0 parallel lines for the RGB interface(RGB mode 1). When RCM [1:0] =’11’ use VSYNC, HSYNC, DOTCLK, DB17-0 parallellines for the RGB interface (RGB mode 2)Pixel clock (DOTCLK) must be running all the time without stopping and it is used toentering VSYNC, HSYNC, DE and DB17-0 lines states when there is a rising edge ofthe DOTCLK.In RGB interface mode 1, the valid display data is inputted in pixel unit via DB17-0according to the high-level(‘H’) of DE signal, and display operations are executed insynchronization with the frame synchronizing signal (VSYNC), line synchronizing signal(HSYNC) and pixel clock (DOTCLK). In RGB interface mode 2, the valid display data isinputted in pixel unit via DB17-0 according to the HBP setting of HSYNC signal, and theVBP setting of VSYNC. In these two RGB interface modes, the input display data is notwritten to GRAM and is displayed directly.Vertical synchronization (VSYNC) signal is used to tell when there a new frame of thedisplay is received , and this is negative (‘-‘, ‘0’, low) active. Horizontal synchronizationsignal (HSYNC) is used to tell when a new line of the frame is received, and this isnegative (‘-‘, ‘0’, low) active. Data enable (DE) is used to tell when RGB information isreceived that should be transferred on the display, and this is positive (‘+’, ‘1’, high)active. DB17-0 are used to tell what the information of the image is, that is transferredon the display when DE=’H’.The pixel clock cycle is described in the following figure.DOTCLKVSYNCHSYNCDEDB17-0Figure 4.31: DOTCLK cycleHimax ConfidentialFor Go-tek OnlyThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.49-October, 2009
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<strong>HX8347</strong>-G(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver4.2 RGB InterfaceDATA SHEET Preliminary V01The <strong>HX8347</strong>-G uses RCM [1:0] =’10’ or ‘11’ Software setting to select RGBinterface. After Power on Sequence, the RGB interface is activated. When RCM [1:0]=’10’ use VSYNC, HSYNC, DE, DOTCLK, DB17-0 parallel lines for the RGB interface(RGB mode 1). When RCM [1:0] =’11’ use VSYNC, HSYNC, DOTCLK, DB17-0 parallellines for the RGB interface (RGB mode 2)Pixel clock (DOTCLK) must be running all the time without stopping and it is used toentering VSYNC, HSYNC, DE and DB17-0 lines states when there is a rising edge ofthe DOTCLK.In RGB interface mode 1, the valid display data is inputted in pixel unit via DB17-0according to the high-level(‘H’) of DE signal, and display operations are executed insynchronization with the frame synchronizing signal (VSYNC), line synchronizing signal(HSYNC) and pixel clock (DOTCLK). In RGB interface mode 2, the valid display data isinputted in pixel unit via DB17-0 according to the HBP setting of HSYNC signal, and theVBP setting of VSYNC. In these two RGB interface modes, the input display data is notwritten to GRAM and is displayed directly.Vertical synchronization (VSYNC) signal is used to tell when there a new frame of thedisplay is received , and this is negative (‘-‘, ‘0’, low) active. Horizontal synchronizationsignal (HSYNC) is used to tell when a new line of the frame is received, and this isnegative (‘-‘, ‘0’, low) active. Data enable (DE) is used to tell when RGB information isreceived that should be transferred on the display, and this is positive (‘+’, ‘1’, high)active. DB17-0 are used to tell what the information of the image is, that is transferredon the display when DE=’H’.The pixel clock cycle is described in the following figure.DOTCLKVSYNCHSYNCDEDB17-0Figure 4.31: DOTCLK cycleHimax ConfidentialFor Go-tek OnlyThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.49-October, 2009