HX8347 - Adafruit

HX8347-G(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver4.1 System interface circuitDATA SHEET Preliminary V01The system interface circuit in HX8347-G supports, 18-/16-/9-/8-bit bus width parallelbus system interface for I80 series CPU, and 4-/3-wire serial bus system interface forserial data input. When NCS = “L”, the parallel and serial bus system interface of theHX8347-G become active and data transfer through the interface circuit is available.The DNC_SCL pin specifies whether the system interface circuit access is to theregister command or to the display data RAM. The input bus format of systeminterface circuit is selected by external pins setting. For selecting the input bus format,please refer to Table 4.1.IM3 IM2 IM1 IM0 InterfaceDNC_ NWR_SData Bus useSCL CL Register/Content GRAM0 0 0 08080 MCU 16-bit paralleltype IDNC NWR D7-D0 D15-D0: 16-bit data0 0 0 18080 MCU 8-bit paralleltype IDNC NWR D7-D0 D7-D0: 8-bit data0 0 1 08080 MCU 16-bit paralleltype IIDNC NWR D8-D1 D17-10, D8-D1: 16-bit data0 0 1 18080 MCU 8-bit paralleltype IIDNC NWR D17-D10 D17-D10: 8-bit data0 1 0 ID 3-wire serial interface - SCL SDA0 1 1 - 4-wire serial interface DNC SCL SDA1 0 0 08080 MCU 18-bit paralleltype IDNC NWR D7-D0 D17-D0: 18-bit data1 0 0 18080 MCU 9-bit paralleltype IDNC NWR D7-D0 D8-D0: 9-bit data1 0 1 08080 MCU 18-bit paralleltype IIDNC NWR D8-D1 D17-D0: 18-bit data1 0 1 18080 MCU 9-bit paralleltype IIDNC NWR D17-D10 D17-D9: 9-bit data1 1 0 ID 3-wire serial interface II - SCL SDI/SDO1 1 1 - 4-wire serial interface II DNC SCL SDI/SDOOther Setting Setting InvalidTable 4.1: Input bus format selection of system interface circuitIt has an Index Register (IR) in HX8347-G to store index data of internal controlregister and GRAM. Therefore, the IR can be written with the index pointer of thecontrol register through data bus by setting DNC_SCL=0. Then the command orGRAM data can be written to register at which that index pointer pointed by settingDNC_SCL=1.Furthermore, there are two 18-bit bus control registers used to temporarily store thedata written to or read from the GRAM. When the data is written into the GRAM fromthe MPU, it is first written into the write-data latch and then automatically written intothe GRAM by internal operation. Data is read through the read-data latch whenreading from the GRAM. Therefore, the first read data operation is invalid and thefollowing read data operations are valid.Himax ConfidentialFor Go-tek OnlyThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.29-October, 2009